Product Info

LTE Standard Module Series
EM05-G Hardware Design
EM05-G_Hardware_Design 42 / 69
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
PCM_DIN
125 μs
MSB
1 2 3231
LSB
Figure 20: Auxiliary Mode Timing
The following table shows the pin definition of PCM interface which can be applied to audio codec design.
Table 12: Pin Definition of PCM Interface
The clock and mode can be configured by AT command, and the default configuration is master mode
using short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See
document [3] for details about AT+QDAI.
Pin No.
Pin Name
I/O
Description
DC Characteristics
20
PCM_CLK
DIO, PD
PCM clock
1.8 V
22
PCM_DIN
DI, PD
PCM data input
1.8 V
24
PCM_DOUT
DO, PD
PCM data output
1.8 V
28
PCM_SYNC
DIO, PD
PCM data frame sync
1.8 V