Service Guide

LTE Standard Module Series
EG91_Series_Hardware_Design
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Table 13: Pin Definition of PCM and I2C Interfaces
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See document [3]
about AT+QDAI for details.
The following figure shows a reference design of PCM interface with external codec IC.
PCM_DIN
PCM_DOUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
Module
1.8 V
4.7K 4.7K
BCLK
LRCK
DAC
ADC
SCL
SDA
BIAS
MICBIAS
INP
INN
LOUTP
LOUTN
Codec
Figure 24: Reference Circuit of PCM Application with Audio Codec
1. It is recommended to reserve an RC (R = 22 Ω, C = 22 pF) circuit on the PCM traces, especially for
PCM_CLK.
2. EG91 series works as a master device pertaining to I2C interface.
Pin Name Pin No. I/O Description Comment
PCM_DIN 6 DI PCM data input
1.8 V power domain.
If unused, keep it open.
PCM_DOUT 7 DO PCM data output
PCM_SYNC 5 DIO PCM data frame sync
1.8 V power domain. In master
mode, it is an output signal. In slave
mode, it is an input signal.
If unused, keep it open.
PCM_CLK 4 DIO PCM data clock
I2C_SCL 40 OD
I2C serial clock (for
external codec)
Require an external pull-up to 1.8 V
If unused, keep it open.
I2C_SDA 41 OD
I2C serial data
(for external codec)
NOTE