Users Manual

LTE Standard Module Series
EC25 Hardware Design
EC25_Hardware_Design
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Figure Index
FIGURE 1: FUNCTIONAL DIAGRAM
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22
FIGURE 2: PIN ASSIGNMENT (TOP VIEW)
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24
FIGURE 3: SLEEP MODE APPLICATION VIA UART
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38
FIGURE 4: SLEEP MODE APPLICATION WITH USB REMOTE WAKEUP
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38
FIGURE 5: SLEEP MODE APPLICATION WITH RI
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39
FIGURE 6: SLEEP MODE APPLICATION WITHOUT SUSPEND FUNCTION
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40
FIGURE 7: POWER SUPPLY LIMITS DURING BURST TRANSMISSION
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41
FIGURE 8: STAR STRUCTURE OF THE POWER SUPPLY
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42
FIGURE 9: REFERENCE CIRCUIT OF POWER SUPPLY
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43
FIGURE 10: TURN ON THE MODULE BY USING DRIVING CIRCUIT
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44
FIGURE 11: TURN ON THE MODULE BY USING KEYSTROKE
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44
FIGURE 12: TIMING OF TURNING ON MODULE
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45
FIGURE 13: TIMING OF TURNING OFF MODULE
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46
FIGURE 14: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT
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47
FIGURE 15: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON
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47
FIGURE 16: TIMING OF RESETTING MODULE
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48
FIGURE 17: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR
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49
FIGURE 18: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR
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49
FIGURE 19: REFERENCE CIRCUIT OF USB APPLICATION
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51
FIGURE 20: REFERENCE CIRCUIT WITH TRANSLATOR CHIP
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53
FIGURE 21: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT
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54
FIGURE 22: PRIMARY MODE TIMING
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55
FIGURE 23: AUXILIARY MODE TIMING
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55
FIGURE 24: REFERENCE CIRCUIT OF PCM AND I2C APPLICATION WITH AUDIO CODEC
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56
FIGURE 25: REFERENCE CIRCUIT OF SD CARD INTERFACE
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57
FIGURE 26: REFERENCE CIRCUIT OF WIRELESS CONNECTIVITY INTERFACES WITH FC20 MODULE
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60
FIGURE 27: SIMPLIFIED BLOCK DIAGRAM FOR ETHERNET APPLICATION
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63
FIGURE 28: REFERENCE CIRCUIT OF SGMII INTERFACE WITH PHY AR8033 APPLICATION
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64
FIGURE 29: REFERENCE CIRCUIT OF THE NETWORK INDICATOR
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65
FIGURE 30: REFERENCE CIRCUITS OF STATUS
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66
FIGURE 31: REFERENCE CIRCUIT OF USB_BOOT INTERFACE
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68
FIGURE 32: TIMING SEQUENCE FOR ENTERING EMERGENCY DOWNLOAD MODE
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68
FIGURE 33: REFERENCE CIRCUIT OF RF ANTENNA INTERFACE
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73
FIGURE 34: MICROSTRIP DESIGN ON A 2-LAYER PCB
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74
FIGURE 35: COPLANAR WAVEGUIDE DESIGN ON A 2-LAYER PCB
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74
FIGURE 36: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND)
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74
FIGURE 37: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND)
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75