Product Info

Automotive Module Series
AG521R-NA QuecOpen Hardware Design
AG521R-NA_QuecOpen_Hardware_Design 8 / 104
Figure Index
Figure 1: Functional Diagram for AG521R-NA QuecOpen
®
.................................................................................... 16
Figure 2: Pin Assignment (Top View) ....................................................................................................................... 18
Figure 3: Sleep Mode Current Consumption Diagram .............................................................................................. 36
Figure 4: Sleep Mode Application with USB Remote Wakeup ................................................................................. 36
Figure 5: Sleep Mode Application without USB Remote Wakeup ............................................................................ 37
Figure 6: Sleep Mode Application without Suspend Function .................................................................................. 38
Figure 7: Power Supply Limits during Burst Transmission ....................................................................................... 39
Figure 8: VBAT Reference Design ............................................................................................................................ 39
Figure 9: 12/24 V Power Supply System Reference Design ..................................................................................... 40
Figure 10: Turn on the Module Using Driving Circuit .............................................................................................. 41
Figure 11: Turn on the Module Using Keystroke ...................................................................................................... 41
Figure 12: Power-on Timing ...................................................................................................................................... 42
Figure 13: Turn on the Module using PON_1 ........................................................................................................... 43
Figure 14: Power-off Timing ..................................................................................................................................... 43
Figure 15: Reference Circuit of RESET by Using Driving Circuit ........................................................................... 45
Figure 16: Reference Circuit of RESET by Using Button ......................................................................................... 45
Figure 17: Timing of Resetting Module .................................................................................................................... 45
Figure 18: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector ...................................... 47
Figure 19: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector ........................................ 47
Figure 20: Reference Circuit of USB 2.0 Application ............................................................................................... 49
Figure 21: Reference Circuit of USB 3.0 Application ............................................................................................... 49
Figure 22: Reference Circuit with Translator Chip.................................................................................................... 51
Figure 23: Reference Circuit with Transistor Circuit ................................................................................................ 52
Figure 24: Reference Circuit of I2S and I2C Application with Audio Codec ........................................................... 53
Figure 25: Reference Design of SDIO Interface for eMMC Application .................................................................. 55
Figure 26: SPI Timing ............................................................................................................................................... 56
Figure 27: Simplified Block Diagram for Ethernet Application ................................................................................ 58
Figure 28: Reference Circuit of RGMII Interface with PHY Application ................................................................. 59
Figure 29: Reference Circuit for Connection with WLAN&BT PHY....................................................................... 62
Figure 30: Reference Circuit of USB_BOOT Interface............................................................................................. 64
Figure 31: Reference Circuit of RF Antenna Interfaces ............................................................................................ 68
Figure 32: Microstrip Design on a 2-layer PCB ........................................................................................................ 68
Figure 33: Coplanar Waveguide Design on a 2-layer PCB........................................................................................ 69
Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) ..................................... 69
Figure 35: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) ..................................... 69
Figure 36: Description of the HFM Connector .......................................................................................................... 71
Figure 37: Referenced Heatsink Design (Heatsink at the Top of the Module) .......................................................... 78
Figure 38: Referenced Heatsink Design (Heatsink at the Backside of Customers’ PCB) ......................................... 78
Figure 39: Module Top and Side Dimensions ........................................................................................................... 80
Figure 40: Module Bottom Dimensions (Top View) ................................................................................................. 81
Figure 41: Recommended Footprint (Top View) ....................................................................................................... 82