Product Info

Automotive Module Series
AG521R-NA QuecOpen Hardware Design
AG521R-NA_QuecOpen_Hardware_Design 55 / 104
R12
NM
R13
NM
R14
NM
R15
NM
R16
NM
R17
NM
R18
NM
R19
NM
R20
10K
R21
47K
VDD_1V8
C1
NM
C2
NM
C3
NM
C4
NM
C5
NM
C6
NM
C7
NM
C8
NM
C9
NM
C10
NM
C11
NM
VDD_3V
C14
100 nF
C15
2.2 µF
VDD_1.8V
C12
100 nF
C13
1 µF
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
CMD
CLK
RSTN
VCCQ
VCC
VSS
eMMC
EMMC_PWR_EN
SDC1_DATA_0
SDC1_DATA_1
SDC1_DATA_2
SDC1_DATA_3
SDC1_DATA_4
SDC1_DATA_5
SDC1_DATA_6
SDC1_DATA_7
SDC1_CMD
SDC1_CLK
EMMC_RST
EMMC_PWR_EN
SDIO_VDD
Module
R1 0R
R2 0R
R3 0R
R4 0R
R5 0R
R6 0R
R7 0R
R8 0R
R9 0R
R10 30-35R
R11 0R
VDD_EXT
Figure 25: Reference Design of SDIO Interface for eMMC Application
Please follow the principles below in eMMC circuit design:
⚫ To avoid jitter of bus, it is recommended to reserve resistors R12–R21 for pulling up SDIOs to
VDD_1.8 V. Resistors R12–R19 are not mounted by default, and the recommended resistor value is
10–100 kΩ.
⚫ In order to improve signal quality, it is recommended to add 0 Ω resistors R1–R9 and R11 in series
between the module and eMMC. Resistor R10 should be 30-35 Ω. The bypass capacitors C1–C11
are reserved and not mounted by default. All resistors and bypass capacitors should be placed close
to the module.
⚫ It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data
trace is 50 Ω (±10%).
⚫ Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits and analog
signals as well as noisy signals such as clock signals and DC-DC signals.
⚫ Spacing DATA to DATA/CLK bus is larger than two times of line width.
⚫ Spacing DATA/CLK/CMD to other signals is larger than two times of line width.
⚫ It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1 mm
and the total routing length less than 50 mm. The total trace length inside the module is 17 mm, so
the exterior total trace length should be less than 33 mm.
⚫ Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of
SDIO bus should be less than 40 pF.