User's Manual
Wi-Fi&Bluetooth Module Series
FC41D_Hardware_Design
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MAIN_TXD
MAIN_RXD
UART_RXD
UART_TXD
Module (DCE)
GND GND
DTE
Figure 6: Main UART Connection Diagram
Through debug tools, the debug UART can be used to output logs for firmware debugging. Its baud rate is
115200 bps by default.
The following is a reference design of debug UART.
Module
DBG_RXD
ESD
DBG_TXD
Test point
Figure 7: Debug UART Reference Crcuit
3.6.2. SPI
FC41D module provides a SPI interface that supports both master and slave modes. The maximum
clock frequency of the interface can reach 50 MHz in slave mode, and the clock frequency is 8 MHz in
the master mode.
In the standard software version of FC41D, SPI does not provide a communication interface.