Product Info

LTE Standard Module Series
EG95 Series Hardware Design
EG95_Series_Hardware_Design
51 / 99
125 μs
PCM_CLK 1 2
PCM_SYNC
31 32
PCM_DOUT
MSB
LSB
MSB
LSB
PCM_DIN
Figure 23: Auxiliary Mode Timing
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Table 14: Pin Definition of PCM and I2C Interfaces
Pin Name
Pin No.
I/O
Description
Comment
PCM_DIN
6
DI
PCM data input
1.8 V power domain
PCM_DOUT
7
DO
PCM data output
1.8 V power domain
PCM_SYNC
5
IO
PCM data frame
synchronization sig
1.8 V power domain
nal
PCM_CLK
4
IO
PCM data bit clock 1.8 V power domain
I2C_SCL
40
OD
An external pull-up to 1.8 V is
I2C serial clock
required.
I2C_SDA
41
OD
An external pull-up to 1.8 V is
I2C serial data
required.
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. Please refer to
document [2] about AT+QDAI command for details.
The following figure shows a reference design of PCM and I2C interfaces with external codec IC.