Product Info

LTE Standard Module Series
EG95 Series Hardware Design
EG95_Series_Hardware_Design
47 / 99
• The main UART interface supports 9600 bps, 19200 bps, 38400 bps, 57600 bps, 115200 bps, 230400
bps, 460800 bps, 921600 bps and 3000000 bps baud rates, and the default is 115200 bps. It supports
RTS and CTS hardware flow control, and is used for AT command communication and data
transmission.
• The debug UART interface supports 115200 bps baud rate. It is used for Linux console and log output.
The following tables show the pin definition of the UART interfaces.
Table 11: Pin Definition of Main UART Interfaces
Pin Name Pin No. I/O Description Comment
RI
DCD
CTS
39
38
36
DO
DO
DO
Ring indicator
Data carrier detection
Clear to send
RTS
37
DI
Request to send
1.8 V power domain
DTR
30
DI
Data terminal ready,
sleep mode control
TXD
35
DO
Transmit data
RXD
34
DI
Receive data
Table 12: Pin Definition of Debug UART Interface
Pin Name
Pin No.
I/O
Description
Comment
DBG_TXD
23
DO
Transmit data
1.8 V power domain
DBG_RXD
22
DI
Receive data
1.8 V power domain
The logic levels are described in the following table.
Table 13: Logic Levels of Digital I/O
Parameter
Min.
Max.
Unit
V
IL
-0.3
0.6
V