Product Info

LTE Standard Module Series
EG95 Series Hardware Design
EG95_Series_Hardware_Design
30 / 99
converter
SPI Interface
1)
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
SPI_CLK
26
DO
Clock signal of SPI
interface
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain.
If unused, keep it
open.
SPI_MOSI
27
DO
Master output slave
input of SPI
interface
V
OL
max = 0.45 V
V
OH
min = 1.35 V
1.8 V power domain.
If unused, keep it
open.
SPI_MISO
28
DI
Master input slave
output of SPI
interface
V
IL
min = -0.3 V
V
IL
max = 0.6 V
V
IH
min = 1.2 V
V
IH
max = 2.0 V
1.8 V power domain.
If unused, keep it
open.
RF Interfaces
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
ANT_GNSS
49
(EG95-
NA/-EX/
-NAX/-
AUX)
AI
GNSS antenna pad
50 Ω impedance.
If unused, keep it
open.
The pin is defined as
ANT_DIV on
EG95-E.
ANT_DIV
49
(EG95-E)
56
(EG95-
AI
Receive diversity
antenna pad
50 Ω impedance.
If unused, keep it
open.
Pin 56 is reserved on
NA/-EX/
EG95-E.
-NAX/-
AUX)
ANT_MAIN
60
IO
Main antenna pad
50 Ω impedance.
Other Pins
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
AP_READY
19
DI
Application
processor sleep
state detection
V
IL
min = -0.3 V
V
IL
max = 0.6 V
V
IH
min = 1.2 V
V
IH
max = 2.0 V
1.8 V power domain.
If unused, keep it
open.