Product Info

Wi-Fi&BT Module Series
FG50V Hardware Design
FG50V_Hardware_Design 31 / 54
3.9.2. WLAN Debug Interface
The following table shows the pin definition of WLAN debug interface. Connect this interface to the test points in
your application.
Table 12: Pin Definition of WLAN Debug Interface
Pin Name Pin No. I/O Description Comment
WLAN_DBG_TXD 21 DO WLAN debug UART transmit
1.8 V power domain.
If unused, keep these pins
open.
WLAN_DBG_RXD 65 DI WLAN debug UART receive
3.9.3. BT Debug Interface
The following table shows the pin definition of BT debug interface. Connect this interface to the test points in
your application.
Table 13: Pin Definition of BT Debug interface
Pin Name Pin No. I/O Description Comment
BT_DBG_TXD 23 DO BT debug UART transmit
1.8 V power domain.
If unused, keep these pins
open.
BT_DBG_RXD 22 DI BT debug UART receive
3.10. RF Antenna Interfaces
The following table shows the pin definition of RF antenna interfaces.
“*” means under development.
NOTE