Product Info

Wi-Fi&BT Module Series
FG50V Hardware Design
FG50V_Hardware_Design 24 / 54
3.5.1. WLAN_EN
WLAN_EN is used to control the WLAN function of FG50V module. WLAN function will be enabled when
WLAN_EN is at high level.
Table 5: Pin Definition of WLAN_EN
3.5.2. PCIe Interface
The following table shows the pin definition of the PCIe interface of FG50V.
Table 6: Pin Definition of PCIe Interface
Pin Name Pin No. I/O Description Comment
WLAN_EN 84 DI WLAN enable
1.8 V power domain.
Active high.
It is suggested to pull down this pin
with a 100 kΩ resistor.
Pin No. I/O Description Comment
PCIE_REFCLK_P 54 AI PCIe reference clock (+)
Require differential
impedance of 85 Ω.
PCIE_REFCLK_M 9 AI PCIe reference clock (-)
PCIE_TX_P 52 AO PCIe transmit (+)
PCIE_TX_M 7 AO PCIe transmit (-)
PCIE_RX_P 56 AI PCIe receive (+)
PCIE_RX_M 11 AI PCIe receive (-)
PCIE_CLKREQ_N 12 DO PCIe clock request
1.8 V power domain.
Active low.
PCIE_RST_N 14 DI PCIe reset
PCIE_WAKE_N 13 DO PCIe wakes up