Product Info

Wi-Fi&BT Module Series
FG50V Hardware Design
FG50V_Hardware_Design 21 / 54
“*” means under development.
3.4. Power Supply
The following table shows the power supply pins and ground pins of FG50V module.
BT_DBG_RXD 22 DI
BT debug UART
receive
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
RF Antenna Interfaces
Pin Name Pin No. I/O
Description DC Characteristics Comment
ANT_WIFI0 28 IO
BT and WLAN
antenna interface
50 Ω impedance.
ANT_WIFI1 33 IO
WLAN antenna
interface
50 Ω impedance.
ANT_BT* 25 IO
Reserved
dedicated BT
antenna interface
50 Ω impedance.
WLAN_SLP_CLK Interface
Pin Name Pin No. I/O
Description DC Characteristics Comment
WLAN_SLP_CLK 15 DI WLAN sleep clock
V
IL
min = -0.3 V
V
IL
max = 0.63 V
V
IH
min = 1.17 V
V
IH
max = 2.1 V
1.8 V power domain.
If unused, keep this pin
open.
RESERVED Interfaces
Pin Name Pin No. I/O
Description DC Characteristics Comment
RESERVED 4, 5, 8, 10, 17, 18, 40, 49, 50, 53, 55, 58, 62, 64, 68, 71–73, 79 Keep these pins open.
NOTE