FG50V Hardware Design Wi-Fi&BT Module Series Version: 1.0 Date: 2020-12-08 Status: Released www.quectel.
Wi-Fi&BT Module Series FG50V Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.htm.
Wi-Fi&BT Module Series FG50V Hardware Design The information contained here is proprietary technical information of Quectel. Transmitting, reproducing, disseminating and editing this document as well as using the content without permission are forbidden. Offenders will be held liable for payment of damages. All rights are reserved in the event of a patent grant or registration of a utility model or design. Copyright © Quectel Wireless Solutions Co., Ltd. 2020. All rights reserved.
Wi-Fi&BT Module Series FG50V Hardware Design About the Document Revision History Version Date Author Description - 2019-11-25 Jared WANG/ Felix FU Creation of the document 1.
Wi-Fi&BT Module Series FG50V Hardware Design Contents About the Document ...................................................................................................................................... 3 Contents ........................................................................................................................................................ 4 Table Index..............................................................................................................................
Wi-Fi&BT Module Series FG50V Hardware Design 4.2. 4.3. 4.4. 4.5. Electrical Characteristics ........................................................................................................................ 38 I/O Interface Characteristics .................................................................................................................. 39 Operating and Storage Temperatures ....................................................................................................
Wi-Fi&BT Module Series FG50V Hardware Design Table Index Table 1: Key Features ................................................................................................................................................. 12 Table 2: I/O Parameters Definition ............................................................................................................................ 17 Table 3: Pin Description ...............................................................................................
Wi-Fi&BT Module Series FG50V Hardware Design Figure Index Figure 1: Functional Diagram of FG50V Module........................................................................................................ 14 Figure 2: Pin Assignment (Top View) ......................................................................................................................... 16 Figure 3: Reference Circuit of power supply from SDX55 platform ...........................................................................
Wi-Fi&BT Module Series FG50V Hardware Design 1 Introduction This document defines the FG50V module and describes its air interfaces and hardware interfaces which are connected with your application. This document can help you quickly understand module interface specifications, electrical and mechanical details, as well as other related information of the module. Associated with application notes and user guides, you can use FG50V module to design and set up applications easily.
Wi-Fi&BT Module Series FG50V Hardware Design A certified modular has the option to use a permanently affixed label, or an electronic label. For a permanently affixed label, the module must be labeled with an FCC ID - Section 2.926 (see 2.2 Certification (labeling requirements) above). The OEM manual must provide clear instructions explaining to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph).
Wi-Fi&BT Module Series FG50V Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating FG50V module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
Wi-Fi&BT Module Series FG50V Hardware Design In locations with explosive or potentially explosive atmospheres, obey all posted signs and turn off wireless devices such as mobile phone or other cellular terminals. Areas with explosive or potentially explosive atmospheres include fuelling areas, below decks on boats, fuel or chemical transfer or storage facilities, and areas where the air contains chemicals or particles such as grain, dust or metal powders.
Wi-Fi&BT Module Series FG50V Hardware Design 2 Product Concept 2.1. General Description FG50V is a Wi-Fi and Bluetooth (BT) module with low power consumption. It is a single-die WLAN (Wireless Local Area Network) and BT combo solution supporting IEEE 802.11a/b/g/n/ac/ax 2.4/5 GHz WLAN standards and BT 5.1* standard, which enables seamless integration of WLAN and BT low energy technologies.
Wi-Fi&BT Module Series FG50V Hardware Design 2.4 GHz 802.11b @ 11 Mbps: 20 dBm 802.11g @ 54 Mbps: 17 dBm 802.11n, HT20 @ MCS7: 16 dBm 802.11n, HT40 @ MCS7: 16 dBm 802.11ax, HE20 @ MCS11: 13 dBm 802.11ax, HE40 @ MCS11: 13 dBm Transmitting Power 5 GHz 802.11a @ 54 Mbps: 15.5 dBm 802.11n, HT20 @ MCS7: 15 dBm 802.11n, HT40 @ MCS7: 15 dBm 802.11ac, VHT20 @ MCS8: 14 dBm 802.11ac, VHT40 @ MCS9: 14 dBm 802.11ac, VHT80 @ MCS9: 14 dBm 802.11ax, HE20 @ MCS11: 13 dBm 802.11ax, HE40 @ MCS11: 13 dBm 802.
Wi-Fi&BT Module Series FG50V Hardware Design 2.3. Functional Diagram The following figure shows a block diagram of FG50V module. VDD_RF VDD_CORE_VL VDD_CORE_VM 5G xFEM VDD_CORE_VH Diplexer ANT_WIFI1 VDD_IO PCIe COEX BB Control BPF 2.4G xFEM BT UART Diplexer ANT_WIFI0 BPF BT PCM Debug UART × 2 Switch/ BT xLNA WLAN_SLP_CLK BPF ANT_BT Optional dedicated BT antenna switch/xLNA 48MHz XO Figure 1: Functional Diagram of FG50V Module 2.4.
Wi-Fi&BT Module Series FG50V Hardware Design 3 Application Interfaces 3.1. General Description FG50V module is equipped with 108 LGA pins that can be connected to the cellular application platform. The subsequent chapters will provide a detailed introduction to the following interfaces and pins of the module: Power supply WLAN interface BT interface* Coexistence interface WLAN_SLP_CLK interface Other interfaces RF antenna interfaces NOTE “*” means under development.
Wi-Fi&BT Module Series FG50V Hardware Design 3.2.
Wi-Fi&BT Module Series FG50V Hardware Design NOTE Please keep all RESERVED pins open. 3.3. Pin Description The following tables show the pin description of FG50V module. Table 2: I/O Parameters Definition Type Description AI Analog Input AO Analog Input DI Digital Input DO Digital Output IO Bidirectional PI Power Input Table 3: Pin Description Power Supply Pin Name VDD_CORE_VL VDD_CORE_VM Pin No. 1, 2, 47 45 FG50V_Hardware_Design I/O Description DC Characteristics Comment PI 0.
Wi-Fi&BT Module Series FG50V Hardware Design VDD_CORE_VH 46 PI 1.95 V power supply for the module’s main part Vmin = 1.85 V Vnorm = 1.95 V Vmax = 2.05 V It must be provided with sufficient current of up to 0.4 A. PI 1.8 V power supply for the module’s I/O pins Vmin = 1.7 V Vnorm = 1.8 V Vmax = 1.9 V It must be provided with sufficient current of up to 0.05 A. PI 3.85 V power supply for the module’s RF part Vmin = 3.3 V Vnorm = 3.85 V Vmax = 4.
Wi-Fi&BT Module Series FG50V Hardware Design BT_EN PCM_DIN* PCM_SYNC* 83 76 35 DI DI DI BT enable VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V 1.8 V power domain. Active high. It is suggested to pull down this pin with a 100 kΩ resistor. PCM data input VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V 1.8 V power domain. PCM data frame sync VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V 1.8 V power domain. 1.8 V power domain.
Wi-Fi&BT Module Series FG50V Hardware Design COEX_TXD COEX_RXD LAA_AS_EN LAA_TXEN 59 16 82 41 DO 2.4G WWAN & WLAN/BT coexistence transmit VOLmax = 0.45 V VOHmin = 1.35 V DI 2.4G WWAN & WLAN/BT coexistence receive VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V DI Allows LAA/n79 to control WLAN xFEM during WLAN sleep mode VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V DI WLAN xFEM control to enable LAA/n79 transmit VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.
Wi-Fi&BT Module Series FG50V Hardware Design 22 DI BT debug UART receive VILmin = -0.3 V VILmax = 0.63 V VIHmin = 1.17 V VIHmax = 2.1 V Pin Name Pin No. I/O Description DC Characteristics ANT_WIFI0 28 IO BT and WLAN antenna interface 50 Ω impedance. ANT_WIFI1 33 IO WLAN antenna interface 50 Ω impedance. ANT_BT* 25 IO Reserved dedicated BT antenna interface 50 Ω impedance. I/O Description DC Characteristics Comment 1.8 V power domain. If unused, keep this pin open.
Wi-Fi&BT Module Series FG50V Hardware Design Table 4: Definition of Power Supply and GND Pins Pin Name Pin No. Description Min. Typ. Max. Unit VDD_CORE_VL 1, 2, 47 0.95 V power supply for the module’s main part 0.9 0.95 1.0 V VDD_CORE_VM 45 1.35 V power supply for the module’s main part 1.28 1.35 1.42 V VDD_CORE_VH 46 1.95 V power supply for the module’s main part 1.85 1.95 2.05 V VDD_IO 43 1.8 V power supply for the module’s I/O pins 1.7 1.8 1.9 V VDD_RF 19, 20, 63 3.
Wi-Fi&BT Module Series FG50V Hardware Design Figure 4: Power Reference Design with Discrete Power Supply Chips 3.5. WLAN Interface The following figure shows the WLAN interface connection between FG50V and the host.
Wi-Fi&BT Module Series FG50V Hardware Design 3.5.1. WLAN_EN WLAN_EN is used to control the WLAN function of FG50V module. WLAN function will be enabled when WLAN_EN is at high level. Table 5: Pin Definition of WLAN_EN Pin Name WLAN_EN Pin No. 84 I/O DI Description Comment WLAN enable 1.8 V power domain. Active high. It is suggested to pull down this pin with a 100 kΩ resistor. 3.5.2. PCIe Interface The following table shows the pin definition of the PCIe interface of FG50V.
Wi-Fi&BT Module Series FG50V Hardware Design The following figure shows the PCIe interface connection between FG50V and the host.
Wi-Fi&BT Module Series FG50V Hardware Design Figure 6: Block Diagram of BT Interface Connection NOTE The GPIO_1 connected to BT_WAKEUP_HOST must be interruptible. 3.6.1. BT_EN BT_EN is used to control the BT function of FG50V module. BT function will be enabled when BT_EN is at high level. Table 7: Pin Definition of BT_EN Pin Name BT_EN Pin No. 83 I/O DI Description Comment BT enable 1.8 V power domain. Active high. It is suggested to pull down this pin with a 100 kΩ resistor. 3.6.2.
Wi-Fi&BT Module Series FG50V Hardware Design Table 8: Pin Definition of BT_WAKEUP_HOST and HOST_WAKEUP_BT Pin Name Pin No. I/O Description Comment BT_WAKEUP_HOST 61 DO BT wakes up host 1.8 V power domain. HOST_WAKEUP_BT 60 DI Host wakes up BT 1.8 V power domain. Externally pull this pin down. NOTE “*” means under development. 3.6.3. PCM Interface* The PCM interface is for audio over Bluetooth phone. The following table shows the pin definition of PCM interface.
Wi-Fi&BT Module Series FG50V Hardware Design Figure 7: PCM Interface Connection NOTE “*” means under development. 3.6.4. UART Interface FG50V supports an HCI UART as defined in Bluetooth Core Specification Version 4.0. In addition, the UART interface also supports software (in-band) sleep control of Bluetooth with Quectel RG50xQ series. You can also choose other 5G modules upon validation tests. If you have any questions, please contact Quectel Technical Support.
Wi-Fi&BT Module Series FG50V Hardware Design 3.7. Conexistence Interface FG50V supports 2.4G WWAN & WLAN/BT coexistence (with coexistence UART) and 5G WWAN & WLAN coexistence. The following table shows the pin definition of coexistence interface. Table 9: Pin Definition of Coexistence Interface Pin Name Pin No. I/O Description COEX_TXD 59 DO 2.4G WWAN & WLAN/BT coexistence transmit COEX_RXD 16 DI 2.
Wi-Fi&BT Module Series FG50V Hardware Design 3.8. WLAN_SLP_CLK Interface The 32.768 kHz clock is used in low power modes, such as IEEE power saving mode and sleep mode. It serves as a timer to determine when to wake up the FG50V module to receive signals in various power saving schemes, and to maintain basic logic operations when the module is in sleep mode. Table 10: Pin Definition of WLAN_SLP_CLK Interface Pin Name Pin No.
Wi-Fi&BT Module Series FG50V Hardware Design NOTE “*” means under development. 3.9.2. WLAN Debug Interface The following table shows the pin definition of WLAN debug interface. Connect this interface to the test points in your application. Table 12: Pin Definition of WLAN Debug Interface Pin Name Pin No. I/O Description Comment WLAN_DBG_TXD 21 DO WLAN debug UART transmit WLAN_DBG_RXD 65 DI WLAN debug UART receive 1.8 V power domain. If unused, keep these pins open. 3.9.3.
Wi-Fi&BT Module Series FG50V Hardware Design Table 14: Pin Definition of RF Antenna Interfaces Pin Name Pin No. I/O Description Comment ANT_WIFI0 28 IO BT and WLAN antenna interface 50 Ω impedance ANT_WIFI1 33 IO WLAN antenna interface 50 Ω impedance ANT_BT* 25 IO Reserved dedicated BT antenna interface 50 Ω impedance NOTE “*” means under development. 3.10.1. Operating Frequency Table 15: Operating Frequency of the Module Feature Frequency Unit 2.4 GHz WLAN 2.400–2.
Wi-Fi&BT Module Series FG50V Hardware Design Figure 10: Reference Circuit for RF Antenna Interfaces 3.10.3. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S).
Wi-Fi&BT Module Series FG50V Hardware Design Figure 12: Coplanar Waveguide Design on a 2-layer PCB Figure 13: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 14: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω.
Wi-Fi&BT Module Series FG50V Hardware Design the ground vias and RF traces should be no less than two times the width of RF signal traces (2 × W). Keep RF traces away from interference sources, and avoid intersection and paralleling between traces on adjacent layers. For more details about RF layout, see document [3]. 3.10.4. Antenna Requirements The following table shows the requirements for antennas. Table 16: Antenna Requirements Type Requirements Frequency Range 2.400–2.4835 GHz 5.180–5.
Wi-Fi&BT Module Series FG50V Hardware Design Figure 15: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 16: Mechanicals of UF.
Wi-Fi&BT Module Series FG50V Hardware Design Figure 17: Space Factor of Mated Connector (Unit: mm) For more details, visit http://www.hirose.com.
Wi-Fi&BT Module Series FG50V Hardware Design 4 Reliability, Radio and Electrical Characteristics 4.1. General Description This chapter mainly introduces electrical and radio characteristics of FG50V module. The details are listed in the subsequent chapters. 4.2. Electrical Characteristics The following table shows the absolute maximum ratings. Table 17: Absolute Maximum Ratings Parameter Min. Max. Unit VDD_CORE_VL -0.3 VDDX + 0.2 V VDD_CORE_VM -0.3 VDDX + 0.2 V VDD_CORE_VH -0.3 VDDX + 0.
Wi-Fi&BT Module Series FG50V Hardware Design The following table shows the recommended operating conditions of the module. Table 18: Recommended Operating Conditions Parameter Min. Typ. Max. Unit VDD_CORE_VL 0.9 0.95 1.0 V VDD_CORE_VM 1.28 1.35 1.42 V VDD_CORE_VH 1.85 1.95 2.05 V VDD_IO 1.7 1.8 1.9 V VDD_RF 3.3 3.85 4.25 V 4.3.
Wi-Fi&BT Module Series FG50V Hardware Design 4.4. Operating and Storage Temperatures Table 20: Operating and storage Temperatures Parameter Min. Typ. Max. Unit Operating Temperature Range 1) -40 25 +85 ºC Storage Temperature Range -40 +95 ºC NOTE 1) Within operating temperature range, the module is IEEE compliant. 4.5. Current Consumption The following tables show the current consumption of the module in different modes. 4.5.1.
Wi-Fi&BT Module Series FG50V Hardware Design 4.5.2. Current Consumption in Normal Operation Table 22: Current Consumption of the Module (Normal Operation, Unit: mA) Description 802.11b 802.11g 802.11n 802.11a 802.11ac VDD_CORE_V VDD_CORE_V VDD_CORE_V VDD_IO VDD_RF L (0.95 V) M (1.35 V) H (1.95 V) (1.8 V) (3.85 V) TX (2.4 GHz) 1 Mbps 460.7 185.5 127.0 2.3 565.1 TX (2.4 GHz) 11 Mbps 501.9 179.7 118.3 2.5 445.1 TX (2.4 GHz) 6 Mbps 460.5 175.9 123.3 2.2 521.3 TX (2.
Wi-Fi&BT Module Series FG50V Hardware Design 802.11ax TX (5 GHz) VHT80 MCS0 571.9 201.7 116.8 2.8 488.7 TX (5 GHz) VHT80 MCS9 570.0 203.1 117.1 2.8 409.6 TX (2.4 GHz) HE20 MCS0 452.0 174.6 120.9 2.4 512.1 TX (2.4 GHz) HE20 MCS11 449.1 174.2 119.7 2.5 441.9 TX (2.4 GHz) HE40 MCS0 481.8 175.4 120.4 2.5 515.3 TX (2.4 GHz) HE40 MCS11 483.4 174.5 119.6 2.4 443.2 TX (5 GHz) HE20 MCS0 430.1 202.0 135.9 2.8 483.8 TX (5 GHz) HE20 MCS11 428.6 201.1 135.1 2.8 393.
Wi-Fi&BT Module Series FG50V Hardware Design 802.11b @ 11 Mbps 17.5 20 dBm 802.11g @ 6 Mbps 15 18.5 dBm 802.11g @ 54 Mbps 14.5 17 dBm 802.11n, HT20 @ MCS0 15 18.5 dBm 802.11n, HT20 @ MCS7 13.5 16 dBm 802.11n, HT40 @ MCS0 15.5 18 dBm 802.11n, HT40 @ MCS7 13.5 16 dBm 802.11ax, HE20 @ MCS0 15.5 18 dBm 802.11ax, HE20 @ MCS11 10.5 13 dBm 802.11ax, HE40 @ MCS0 15.5 18 dBm 802.11ax, HE40 @ MCS11 10.5 13 dBm Table 24: Conducted RF Output Power at 5 GHz Frequency Min.
Wi-Fi&BT Module Series FG50V Hardware Design 802.11ac, VHT80 @ MCS9 11.5 14 dBm 802.11ax, HE20 @ MCS0 15 17.5 dBm 802.11ax, HE20 @ MCS11 10.5 13 dBm 802.11ax, HE40 @ MCS0 15 17.5 dBm 802.11ax, HE40 @ MCS11 10.5 13 dBm 802.11ax, HE80 @ MCS0 15 17.5 dBm 802.11ax, HE80 @ MCS11 10.5 13 dBm 4.6.2. Conducted RF Receiving Sensitivity Table 25: Conducted RF Receiving Sensitivity at 2.4 GHz Frequency Receiving Sensitivity (Typ.) 802.11b @ 1 Mbps -96 dBm 802.
Wi-Fi&BT Module Series FG50V Hardware Design Table 26: Conducted RF Receiving Sensitivity at 5 GHz Frequency Receiving Sensitivity (Typ.) 802.11a @ 6 Mbps -94 dBm 802.11a @ 54 Mbps -75 dBm 802.11n, HT20 @ MCS0 -93 dBm 802.11n, HT20 @ MCS7 -75 dBm 802.11n, HT40 @ MCS0 -91 dBm 802.11n, HT40 @ MCS7 -72 dBm 802.11ac, VHT20 @ MCS0 -94 dBm 802.11ac, VHT20 @ MCS8 -72 dBm 802.11ac, VHT40 @ MCS0 -92 dBm 802.11ac, VHT40 @ MCS9 -67 dBm 802.11ac, VHT80 @ MCS0 -89 dBm 802.
Wi-Fi&BT Module Series FG50V Hardware Design The following table shows the module electrostatic discharge characteristics. Table 27: Electrostatic Discharge Characteristics Tested Points Contact Discharge Air Discharge Unit VDD_RF, GND ±6 ±10 kV Antenna Interfaces ±6 ±10 kV Other Interfaces ±0.
Wi-Fi&BT Module Series FG50V Hardware Design 5 Mechanical Dimensions This chapter describes the mechanical dimensions of FG50V module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 5.1.
Wi-Fi&BT Module Series FG50V Hardware Design Pin1 Figure 19: FG50V Bottom Dimension (Bottom View) NOTE The package warpage level of the module conforms to JEITA ED-7306 standard.
Wi-Fi&BT Module Series FG50V Hardware Design 5.2. Recommended Footprint Pin1 Figure 20: Recommended Footprint (Top View) NOTES 1. For easy maintenance of this module, keep at least 3 mm between the module and other components on the motherboard. 2. Keep all RESERVED pins open.
Wi-Fi&BT Module Series FG50V Hardware Design 5.3. Top and Bottom Views of the Module Figure 21: Top View of the Module Figure 22: Bottom View of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel.
Wi-Fi&BT Module Series FG50V Hardware Design 6 Storage, Manufacturing and Packaging 6.1. Storage The module is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35–60 %. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3.
Wi-Fi&BT Module Series FG50V Hardware Design 1. 1) This floor life is only applicable when the environment conforms to IPC/JEDEC J-STD-033. 2. To avoid blistering, layer separation and other soldering issues, it is forbidden to expose the modules to the air for a long time. If the temperature and moisture do not conform to IPC/JEDEC J-STD-033 or the relative moisture is over 60%, it is recommended to start the solder reflow process within 24 hours after the package is removed.
Wi-Fi&BT Module Series FG50V Hardware Design Soak Zone Max slope 1–3 °C/s Soak time (between A and B: 150 °C and 200 °C) 70–120 s Reflow Zone Max slope 2–3 °C/s Reflow time (D: over 220 °C) 45–70 s Max temperature 238 °C to 246 °C Cooling down slope -1.5 to -3 °C/s Reflow Cycle Max reflow cycle 1 6.3. Packaging FG50V is packaged in tape and reel carriers. Each reel is 330 mm in diameter and contains 200 modules.
Wi-Fi&BT Module Series FG50V Hardware Design 7 Appendix References Table 29: Related Documents SN Document Name Description [1] Quectel_5G_EVB_User_Guide EVB user guide for Quectel 5G modules [2] Quectel_FG50V_Reference_Design FG50V reference design [3] Quectel_RF_Layout_Application_Note RF layout application note [4] Quectel_RG500Q_Series_Wi-Fi_Application_Note FG50V Wi-Fi_application note [5] Quectel_Module_Secondary_SMT_Application_Note Module secondary SMT application note Table 30:
Wi-Fi&BT Module Series FG50V Hardware Design HE High Efficiency HT High Throughput IEEE Institute of Electrical and Electronics Engineers IIL Input Leakage Current I/O Input/Output LNA Low-Noise Amplifier LTE Long Term Evolution Mbps Megabits per second MCS Modulation and Coding Scheme MOQ Minimum Order Quantity PA Power Amplifier PCB Printed Circuit Board PCM Pulse Code Modulation QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RoHS
Wi-Fi&BT Module Series FG50V Hardware Design VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOHmin Minimum Output High Level Voltage Value VSWR Voltage Standing Wave Ratio Wi-Fi Wireless-Fidelity WLAN Wireless Local Area Network FG50V_Hardware_Design 56 / 54