Product Info

5G Module Series
RM505Q-AE Hardware Design
RM505Q-AE_Hardware_Design 7 / 79
Figure Index
Figure 1: Functional Block Diagram ........................................................................................................... 15
Figure 2: Pin Assignment ........................................................................................................................... 17
Figure 3: Power Supply Limits during Radio Transmission ....................................................................... 23
Figure 4: Reference Circuit for VCC Pins .................................................................................................. 24
Figure 5: Reference Design of Power Supply ............................................................................................ 24
Figure 6: Turn-on Timing of the Module ..................................................................................................... 25
Figure 7: Turn on the Module with a Host GPIO ........................................................................................ 26
Figure 8: Turn-off Timing through FULL_CARD_POWER_OFF# ............................................................. 27
Figure 9: Turn-off Timing through AT Command and FULL_CARD_POWER_OFF# .............................. 27
Figure 10: Reference Circuit for RESET_N with NPN Driving Circuit ....................................................... 28
Figure 11: Reference Circuit for RESET_N with NMOS Driving Circuit .................................................... 29
Figure 12: Reference Circuit for RESET_N with Button ............................................................................ 29
Figure 13: Resetting Timing of the Module ................................................................................................ 30
Figure 14: Reference Circuit for Normally Closed (U)SIM Card Connector .............................................. 31
Figure 15: Reference Circuit for Normally Open (U)SIM Card Connector ................................................ 32
Figure 16: Reference Circuit for a 6-Pin (U)SIM Card Connector ............................................................. 32
Figure 17: Reference Circuit for USB 3.1/2.0 Interface ............................................................................. 34
Figure 18: PCIe Interface Reference Circuit .............................................................................................. 36
Figure 19: PCIe Power-on Timing Requirements of M.2 Specification ..................................................... 37
Figure 20: PCIe Power-on Timing Requirements of the Module ............................................................... 37
Figure 21: Primary Mode Timing ................................................................................................................ 39
Figure 22: Auxiliary Mode Timing .............................................................................................................. 40
Figure 23: W_DISABLE1# and W_DISABLE2# Reference Circuit ........................................................... 43
Figure 24: WWAN_LED# Reference Circuit .............................................................................................. 43
Figure 25: WAKE_ON_WAN# Signal Reference Circuit ........................................................................... 44
Figure 26: Recommended Circuit for Configuration Pins .......................................................................... 47
Figure 27: Antenna Connectors on the Module ......................................................................................... 50
Figure 28: Reference Circuit of GNSS Antenna ........................................................................................ 54
Figure 29: Reference Design for Cellular Antenna .................................................................................... 55
Figure 30: Microstrip Design on a 2-layer PCB ......................................................................................... 56
Figure 31: Coplanar Waveguide Design on a 2-layer PCB ....................................................................... 56
Figure 32: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) .................... 56
Figure 33: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) .................... 57
Figure 34: RM505Q-AE RF Connector Dimensions (Unit: mm) ................................................................ 58
Figure 35: Specifications of Mating Plugs Using Ø 0.81 mm Coaxial Cables ........................................... 59
Figure 36: Connection between RF Connector and Mating Plug Using Ø 0.81 mm Coaxial Cable ......... 60
Figure 37: Connection between RF Connector and Mating Plug Using Ø 1.13 mm Coaxial Cable ......... 60
Figure 38: Thermal Dissipation Area on Both Sides of Module (Unit: mm) ............................................... 72
Figure 39: Mechanical Dimensions of RM505Q-AE (Unit: mm) ................................................................ 74
Figure 40: TOP & Bottom View of the Module ........................................................................................... 75
Figure 41: Tray Size (Unit: mm) ................................................................................................................. 76