RM505Q-AE Hardware Design 5G Module Series Version: 1.0.0 Date: 2020-12-14 Status: Preliminary www.quectel.
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5G Module Series RM505Q-AE Hardware Design About the Document Revision History Version Date Author Description - 2020-10-20 Jared WANG Hank LIU Creation of the document 2020-12-14 Jared WANG/ Simon WANG/ Hank LIU Preliminary 1.0.
G Module Series RM505Q-AE Hardware Design Contents About the Document ................................................................................................................................... 3 Contents ....................................................................................................................................................... 4 Table Index ...................................................................................................................................
5G Module Series RM505Q-AE Hardware Design 4 GNSS Receiver ................................................................................................................................... 48 4.1. General Description .................................................................................................................. 48 4.2. GNSS Performance .................................................................................................................. 48 5 Antenna Interfaces...........
5G Module Series RM505Q-AE Hardware Design Table Index Table 1: Frequency Bands and GNSS Systems of RM505Q-AE Module ................................................. 11 Table 2: Key Features of RM505Q-AE ...................................................................................................... 12 Table 3: Definition of I/O Parameters......................................................................................................... 18 Table 4: Pin Description .............................
5G Module Series RM505Q-AE Hardware Design Figure Index Figure 1: Functional Block Diagram ........................................................................................................... 15 Figure 2: Pin Assignment ........................................................................................................................... 17 Figure 3: Power Supply Limits during Radio Transmission .......................................................................
5G Module Series RM505Q-AE Hardware Design Figure 42: Tray Packaging Procedure .......................................................................................................
5G Module Series RM505Q-AE Hardware Design 1 Introduction This document introduces RM505Q-AE module and describes its air interface and hardware interfaces which are connected with customers’ applications. This document helps you quickly understand the interface specifications, electrical and mechanical details, as well as other related information of the module. To facilitate its application in different fields, reference design is also provided for reference.
5G Module Series RM505Q-AE Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
5G Module Series RM505Q-AE Hardware Design 2 Product Concept 2.1. General Description RM505Q-AE is a 5G NR/LTE-A/UMTS/HSPA+ wireless communication module with receive diversity. It provides data connectivity on 5G NR SA and NSA, LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA and WCDMA networks and a standard PCI Express M.2 interface. It supports embedded operating systems such as Windows, Linux and Android, and also provides GNSS and voice functionality to meet specific application demands.
5G Module Series RM505Q-AE Hardware Design ⚫ ⚫ ⚫ Smart metering system Wireless router and switch Other wireless terminal devices 2.2. Key Features The following table describes key features of RM505Q-AE. Table 2: Key Features of RM505Q-AE Feature Details Function Interface ⚫ PCI Express M.2 Interface Power Supply ⚫ ⚫ Supply voltage: 3.135–4.4 V Typical supply voltage: 3.
5G Module Series RM505Q-AE Hardware Design ⚫ ⚫ ⚫ ⚫ Support QPSK, 16QAM and 64QAM modulation DC-HSDPA: Max 42 Mbps (DL) HSUPA: Max 5.76 Mbps (UL) WCDMA: Max 384 kbps (DL)/384 kbps (UL) Internet Protocol Features ⚫ ⚫ QMI/NTP* protocols The protocols PAP and EIRP usually used for PPP connections SMS ⚫ ⚫ ⚫ ⚫ Text and PDU modes Point-to-point MO and MT SMS cell broadcast SMS storage: ME by default (U)SIM Interfaces ⚫ ⚫ ⚫ Support (U)SIM card: Class B (3.0 V) and Class C(1.
5G Module Series RM505Q-AE Hardware Design NOTES 1. 2. 3. 4. 1) HPUE is only for single carrier. To meet this operating temperature range, you need to ensure effective thermal dissipation, for example, by adding passive or active heatsinks, heat pipes, vapor chambers, etc. Within this range, the module can meet 3GPP specifications.
5G Module Series RM505Q-AE Hardware Design 2.3. Functional Diagram The following figure shows the functional block diagram of RM505Q-AE. VCC GND ET PMIC FULL_CARD_POWER_OFF# 38.4M XO SPMI (U)SIM2 Tx (U)SIM1 IQ PCIe × 1 RFFE Baseband GPIOs Control WWAN_LED# WAKE_ON_WAN# Tx/Rx Blocks PRx USB 2.0 & USB 3.1 Sub-6 GHz Transceiver PCI Express M.
5G Module Series RM505Q-AE Hardware Design 3 Application Interfaces The physical connections and signal levels of RM505Q-AE comply with PCI Express M.2 specification.
5G Module Series RM505Q-AE Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of RM505Q-AE. The top side contains RM505Q-AE module and antenna connectors. No.
5G Module Series RM505Q-AE Hardware Design 3.2. Pin Description Table 3: Definition of I/O Parameters Type Description AI Analog Input AO Analog Output DI Digital Input DO Digital Output IO Bidirectional OD Open Drain PI Power Input PO Power Output The following table shows the pin definition and description of RM505Q-AE. Table 4: Pin Description Pin No.
5G Module Series RM505Q-AE Hardware Design turned off. When it is at high voltage level, the module is turned on. 7 USB_DP AI, AO USB differential data (+) Requires differential impedance of 90 Ω 8 W_DISABLE1# DI Airplane mode control. 1.8/3.3 V power domain. Active LOW. 9 USB_DM AI, AO USB differential data (-) Requires differential impedance of 90 Ω 10 WWAN_LED#* OD RF status indication LED Open drain and active low signal.
5G Module Series RM505Q-AE Hardware Design 28 PCM_SYNC* IO PCM data frame sync 1.8 V power domain 29 USB_SS_TX_M AO USB 3.1 super-speed transmit (-) Requires differential impedance of 90 Ω 30 USIM1_RST DO (U)SIM1 card reset 1.8/3.0 V power domain 31 USB_SS_TX_P AO USB 3.1 super-speed transmit (+) Requires differential impedance of 90 Ω 32 USIM1_CLK DO (U)SIM1 card clock 1.8/3.0 V power domain 33 GND 34 USIM1_DATA IO (U)SIM1 card data 1.8/3.
5G Module Series RM505Q-AE Hardware Design 51 GND Ground 52 PCIE_CLKREQ_N OD 53 54 PCIe clock request. Open drain Active LOW. PCIE_REFCLK_M AI, AO PCIe reference clock (-) 100 MHz. Requires differential impedance of 85 Ω PCIE_WAKE_N OD PCIe wake up. Open drain Active LOW. 55 PCIE_REFCLK_P AI, AO PCIe reference clock (+) 100 MHz. Requires differential impedance of 85 Ω 56 RFFE_CLK* DO Used for external MIPI IC control 1.
5G Module Series RM505Q-AE Hardware Design Vnorm = 3.7 V Vmax = 4.4 V 71 GND Ground 72 VCC PI Power supply 73 GND 74 VCC PI Power supply 75 CONFIG_2 DO Not connected internally Vmin = 3.135 V Vnorm = 3.7 V Vmax = 4.4 V Ground Vmin = 3.135 V Vnorm = 3.7 V Vmax = 4.4 V NOTES 1. “*” means under development. 、 2. Keep all NC, reserved and unused pins unconnected. 3.3. Operating Modes The table below briefly summarizes various operating modes to be mentioned in the following chapters.
5G Module Series RM505Q-AE Hardware Design In this mode, the power management unit shuts down the power supply. Software is inactive, the serial interfaces are inaccessible, and the operating voltage (connected to VCC) remains applied. Power Down Mode 3.4. Power Supply The following table shows pin definition of VCC pins and ground pins. Table 6: Definition of VCC and GND Pins Pin No. Pin Name I/O Power Domain Description 2, 4, 70, 72, 74 VCC PI 3.135–4.4 V 3.
5G Module Series RM505Q-AE Hardware Design circuit for the VCC. Module VCC VCC 2, 4, 70, 72, 74 D1 5.1 V + C1 100 μF C2 1 μF C3 C4 C5 100 nF 33 pF 10 pF PMU 3, 5, 11, 27, GND 33, 39, 45, 51, 57, 71, 73 Figure 4: Reference Circuit for VCC Pins 3.4.2. Reference Design for Power Supply Power design is critical as the module’s performance largely depends on its power source. The power supply of the module should be able to provide a sufficient current of 3.0 A at least.
5G Module Series RM505Q-AE Hardware Design 3.5. Turn on and off Scenarios 3.5.1. Turn on the Module FULL_CARD_POWER_OFF# asynchronous signal is an active low input that is used to turn on/off the entire module. When the input signal is asserted high (≥ 1.19 V) the module will be turned on. When the input signal is driven low (≤ 0.2 V) or Tri-stated, the module will be shut down. This input signal is 3.3-V-tolerant and can be driven by either 1.8 V or 3.3 V GPIO.
5G Module Series RM505Q-AE Hardware Design It is recommended to use a host GPIO to control FULL_CARD_POWER_OFF# to turn on the module. A simple reference circuit is illustrated as the following figure. Host Module 1.8 V or 3.3 V FULL_CARD_POWER_OFF# GPIO 6 R4 100k PMU Note: The voltage of pin 6 should be no less than 1.19 V when it is at HIGH level. Figure 7: Turn on the Module with a Host GPIO NOTES 1. 2. 3. 4. tpower-on is the interval between VCC and RESET_N high voltage level.
5G Module Series RM505Q-AE Hardware Design VCC RESET_N(H) FULL_CARD_POWER_OFF# ≥10 s Module Status RUNNING Power-off procedure OFF Figure 8: Turn-off Timing through FULL_CARD_POWER_OFF# 3.5.2.2. Turn off the Module through AT Command It is also a safe way to use AT+QPOWD command to turn off the module. For more details about the command, see document [2]. The module is designed to be turned on with a host GPIO.
5G Module Series RM505Q-AE Hardware Design the module will be immediately placed in a Power On Reset (POR) condition. CAUTION: Triggering the RESET# signal will lead to the loss of all data in the modem and the removal of system drivers. It will also disconnect the modem from the network. Table 8: Definition of RESET_N Pin Pin No. 67 Pin Name RESET_N Description DC Characteristics Comment Reset the module VIH(max) = 1.5 V VIH(min) = TBD VIL(max) = TBD Internally pulled up to 1.
5G Module Series RM505Q-AE Hardware Design Host Module VDD 1.5 V R1 100K RESET_N Reset pulse GPIO R4 10R 67 Reset Logic Q2 NMOS R5 100K 200-700 ms Figure 11: Reference Circuit for RESET_N with NMOS Driving Circuit Module VDD 1.5 V R1 100K RESET_N 67 Reset Logic S1 TVS C1 33 pF 200-700 ms Note: The capacitor C1 is recommended to be less than 47 pF. Figure 12: Reference Circuit for RESET_N with Button The timing of reset scenario is illustrated in the following figure.
5G Module Series RM505Q-AE Hardware Design VCC ≤ 700 ms ≥ 200 ms RESET_N VIL ≤ 0.5 V Module Status Running Resetting Restart Figure 13: Resetting Timing of the Module 3.7. (U)SIM Interfaces The (U)SIM interfaces circuitry meets ETSI and IMT-2000 requirements. Both Class B (3.0 V) and Class C (1.8 V) (U)SIM cards are supported, and Dual SIM Single Standby* function is supported. Table 9: Pin Definition of (U)SIM Interfaces Pin No.
5G Module Series RM505Q-AE Hardware Design NOTE “*” means under development. RM505Q-AE supports (U)SIM card hot-plug via the USIM_DET pin. With a normally closed (U)SIM card connector, the USIM_DET is normally short-circuited to ground when a (U)SIM card is not inserted, and the USIM_DET will change from low to high voltage level when a (U)SIM card is inserted. The rising edge indicates an insertion of the (U)SIM card. When the (U)SIM card is removed, USIM_DET will change from high to low voltage level.
5G Module Series RM505Q-AE Hardware Design USIM_VDD Module USIM_CLK 100 nF 10-20k USIM_VDD USIM_RST (U)SIM Card Connector VCC 22R 1.8 V RST 22R CLK USIM_DET 4.7k CD2 CD1 22R 33 pF GND 33 pF IO 33 pF USIM_DATA VPP 33k GND TVS Note: All these resistors, capacitors and TVS should be close to (U)SIM card connector in PCB layout. Figure 15: Reference Circuit for Normally Open (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET disconnected.
5G Module Series RM505Q-AE Hardware Design ⚫ ⚫ ⚫ ⚫ potential. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground. To offer better ESD protection, add a TVS diode array of which the parasitic capacitance should be not higher than 10 pF. Add 22 Ω resistors in series between the module and the (U)SIM card connector to suppress EMI such as spurious transmission, and to enhance ESD protection.
5G Module Series RM505Q-AE Hardware Design For more details about the USB 3.1 & 2.0 specifications, please visit http://www.usb.org/home. The USB 2.0 interface is recommended to be reserved for firmware upgrade in designs. The following figure shows a reference circuit for USB 3.1/2.0 interface.
5G Module Series RM505Q-AE Hardware Design 3.9. PCIe Interface RM505Q-AE provides one integrated PCIe (Peripheral Component Interconnect Express) interface which complies with the PCI Express Base Specification, Revision 3.0 and supports up to 8 Gbps per lane. ⚫ ⚫ PCI Express Base Specification, Revision 3.0 compliant Data rate up to 8 Gbps per lane The following table presents the pin definition of PCIe interface. Table 11: Pin Definition of PCIe Interface Pin No.
5G Module Series RM505Q-AE Hardware Design Host Module PCIE_REFCLK_P PCIE_REFCLK_M R4 0R PCIE_REFCLK_P 55 R5 0R PCIE_REFCLK_M 53 PCIE_TX_P C5 220 nF PCIE_RX_P 49 PCIE_TX_M C6 220 nF PCIE_RX_M 47 PCIE_TX_P 43 C1 220 nF PCIE_TX_M 41 C2 220 nF PCIE_RX_P PCIE_RX_M BB VCC_IO_HOST R1 100k PCIE_WAKE_N PCIE_CLKREQ_N PCIE_RST_N R2 100k R3 100k PCIE_WAKE_N 54 PCIE_CLKREQ_N 52 PCIE_RST_N 50 Note: The voltage level of VCC_IO_HOST depends on the host side due to the open drain in pins
5G Module Series RM505Q-AE Hardware Design Figure 19: PCIe Power-on Timing Requirements of M.2 Specification Module power-on or insertion detection VCC tpower -on FUL L_CARD_ POWER_OFF System turn-on and booting RESET_N RFFE_ VIO _1V8 tturn-on VIH 1.19 V 68 ms 23 ms TPVPGL 100 ms PICE_RST_N TPERST#_CLK ＞ 100 us PICE_REFCL K Figure 20: PCIe Power-on Timing Requirements of the Module The following principles of PCIe interface design should be complied with, so as to meet PCIe specification.
5G Module Series RM505Q-AE Hardware Design ⚫ You must not route PCIe data traces under components or cross them with other traces. 3.9.2. USB and PCIe Modes RM505Q-AE supports to communicate through both USB and PCIe interfaces, respectively referring to the USB mode and the PCIe mode, as described below: USB Mode ⚫ ⚫ ⚫ Supports all USB 2.0/3.
5G Module Series RM505Q-AE Hardware Design 3.10. PCM Interface* RM505Q-AE supports audio communication via Pulse Code Modulation (PCM) digital interface. The PCM interface supports the following modes: ⚫ ⚫ Primary mode (short frame synchronization): the module works as both master and slave. Auxiliary mode (long frame synchronization): the module works as master only. In the primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge.
5G Module Series RM505Q-AE Hardware Design 125 μs 1 PCM_CLK 2 31 32 PCM_SYNC MSB LSB MSB LSB PCM_DOUT PCM_DIN Figure 22: Auxiliary Mode Timing The following table shows the pin definition of PCM interface which can be applied to audio codec design. Table 12: Pin Definition of PCM Interface Pin No. Pin Name I/O Description Comment 20 PCM_CLK IO PCM data bit clock 1.8 V power domain In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open.
5G Module Series RM505Q-AE Hardware Design 3.11. Control and Indication Interfaces The following table shows the pin definition of control and indication pins. Table 13: Pin Definition of Control and Indication Interfaces Pin No. Pin Name I/O Description Comment 8 W_DISABLE1# DI Airplane mode control. 1.8/3.3 V power domain Active LOW. 10 WWAN_LED#* OD Indicate RF status of the module. Open drain and active low signal. 23 WAKE_ON_WAN# OD Wake up the host.
5G Module Series RM505Q-AE Hardware Design Table 14: RF Function Status W_DISABLE1# Logic Level AT Commands RF Function Status High AT+CFUN=1 Enabled High AT+CFUN=0 AT+CFUN=4 Disabled Low AT+CFUN=0 AT+CFUN=1 AT+CFUN=4 Disabled 3.11.2. W_DISABLE2# RM505Q-AE provides a W_DISABLE2# pin to disable or enable the GNSS function. The W_DISABLE2# pin is pulled up by default. Driving it low will disable the GNSS function. The combination of W_DISABLE2# pin and AT commands controls the GNSS function.
5G Module Series RM505Q-AE Hardware Design Host Module VCC_IO_HOST VDD 1.8 V R5 10k R6 10k GPIO GPIO R2 100k W_DISABLE2# 26 W_DISABLE1# 8 R3 100k BB Note: The voltage level of VCC_IO_HOST could be 1.8 V or 3.3 V typically. Figure 23: W_DISABLE1# and W_DISABLE2# Reference Circuit 3.11.3. WWAN_LED#* The WWAN_LED# signal is used to indicate the RF status of the module, and its sink current is up to 10 mA.
5G Module Series RM505Q-AE Hardware Design Table 16: Network Status Indications of WWAN_LED# Signal WWAN_LED# Logic Level Description Low (LED on) RF function is turned on High (LED off) RF function is turned off if any of the following occurs: ⚫ The (U)SIM card is not powered. ⚫ W_DISABLE1# is at low voltage level (airplane mode enabled). ⚫ AT+CFUN=4 (RF function disabled). 3.11.4. WAKE_ON_WAN# The WAKE_ON_WAN# is an open drain pin, which requires a pull-up resistor on the host.
5G Module Series RM505Q-AE Hardware Design 3.11.5. DPR* RM505Q-AE provides a DPR (Dynamic Power Reduction) pin for body SAR (Specific Absorption Rate) detection. The signal is sent from the proximity sensor of a host system to RM505Q-AE module to provide an input trigger, which will reduce the output power in radio transmission. Table 18: Function of the DPR Signal DPR Level Function High/Floating NO max. transmitting power backoff Low Max.
5G Module Series RM505Q-AE Hardware Design 60 WLAN_TX_EN DI Notification from WLAN to SDR while transmitting 1.8 V power domain NOTE “*” means under development. 3.13. Antenna Tuner Control Interface* ANTCTL[1:2] and RFFE signals are used for antenna tuner control and should be routed to an appropriate antenna control circuit. More details about the interface will be added in the future version of this document. Table 20: Pin Definition of Antenna Tuner Control Interface Pin No.
5G Module Series RM505Q-AE Hardware Design 3.14. Configuration Pins RM505Q-AE provides four configuration pins, which are defined as below. Table 21: Definition of Configuration Pins Pin No. Pin Name I/O Power Domain Description 21 CONFIG_0 DO 0 Not connected internally 69 CONFIG_1 DO 0 Connected to GND internally 75 CONFIG_2 DO 0 Not connected internally 1 CONFIG_3 DO 0 Not connected internally The following figure shows a reference circuit for these four pins.
5G Module Series RM505Q-AE Hardware Design 4 GNSS Receiver 4.1. General Description RM505Q-AE includes a fully integrated global navigation satellite system solution that supports Gen9-Lite of Qualcomm (GPS, GLONASS, BeiDou/Compass, and Galileo). The module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via USB interface by default. The GNSS engine is switched off by default. It has to be switched on via AT command.
5G Module Series RM505Q-AE Hardware Design Hot start @ open sky Accuracy (GNSS) CEP-50 Autonomous TBD s XTRA enabled TBD s Autonomous @ open sky TBD m NOTES 1. 2. 3. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain locked (keep positioning for at least 3 minutes continuously). Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain locked within 3 minutes after the loss of lock.
5G Module Series RM505Q-AE Hardware Design 5 Antenna Interfaces RM505Q-AE provides five antenna interfaces, the impedance of each antenna port is 50 Ω. 5.1. Antenna Connectors The ANT0, ANT1, ANT2,ANT3 and ANT4_GNSS antenna connectors are shown by the following figure.
5G Module Series RM505Q-AE Hardware Design Table 24: RF Bands Supported by RM505Q-AE Antenna Connectors Pin Name ANT0 ANT1 ANT2 ANT3 ANT4_ GNSS I/O Description Comment AI/AO LTE MHB TRx0; LTE UHB PRx MIMO 5G FDD/TDD MHB TRx0; 5G NR n77/n78/n79 PRx MIMO; 50 Ω impedance AI/AO LTE LB TRx0; LTE MHB DRx MIMO; LTE B46 PRx; LTE UHB DRx MIMO 5G FDD LB TRx0; 5G FDD/TDD MHB DRx MIMO; 5G NR n77/n78/n79 DRx MIMO; 50 Ω impedance AI/AO LTE LB DRx; LTE MHB PRx MIMO; 5G NR n77/n78/n41/n79 TRx0; LTE UHB TRx
5G Module Series RM505Q-AE Hardware Design LTE UHB DRx MIMO; 5G FDD LB TRx0; 5G FDD/TDD MHB DRx MIMO; 5G NR n77/n78/n79 DRx MIMO; ANT2 ANT3 ANT4_ GNSS AI/AO LTE LB DRx; LTE MHB PRx MIMO; 5G NR n77/n78/n41/n79 TRx0; LTE UHB TRx0; 5G FDD LB DRx; 5G FDD MHB PRx MIMO; 50 Ω impedance AI/AO LTE MHB DRx;LTE B46 DRx LTE UHB DRx; 5G FDD/TDD MHB DRx; 5G NR n77/n78/n79 DRx; 50 Ω impedance AI GNSS L1 & L5 Rx 50 Ω impedance 5.3.
5G Module Series RM505Q-AE Hardware Design B17 704–716 734–746 B17 – – – B18 815–830 860–875 B18 – – – B19 830–845 875–890 B19 – B19 – EU800 832–862 791–821 B20 – – n20 PCS + G 1850–1915 1930–1995 B25 – – n25 B26 814–849 859–894 B26 – – – 700 APAC 703–748 758–803 B28 – – n28 FLO – 717–728 B29 – – – WCS 2305–2315 2350–2360 B30 – – – L-band – 1452–1496 B32 – – – B34 2010–2025 2010–2025 – B34 – – B38 2570–2620 2570–2620 – B38 –
5G Module Series RM505Q-AE Hardware Design Table 27: GNSS Frequency Type Frequency Unit GPS/Galileo/QZSS 1575.42±1.023 (GPS L1) 1176.45±10.23 (GPS L5) MHz Galileo 1575.42 ±2.046 (E1) MHz QZSS 1575.42 (L1) MHz GLONASS 1597.5–1605.8 MHz BeiDou 1561.098 ±2.046 MHz VDD 1.7 V 18R GNSS Antenna 47 nH ANT4_GNSS 56 pF GPS matching ESD Protector Figure 28: Reference Circuit of GNSS Antenna NOTES 1. 2. 3. 4. 5.
5G Module Series RM505Q-AE Hardware Design 5.5. Reference Design for Cellular Antenna Interfaces A reference design for cellular antenna interface is shown as below. A π-type matching circuit should be reserved for better cellular RF performance. The capacitors are not mounted by default. R1 0R ANT0 C1 C2 R4 0R ANT3 C7 C8 R5 0R ANT4_GNSS C9 C10 Figure 29: Reference Design for Cellular Antenna NOTES 1. 2. 3. 4. 5. Keep the characteristic impedance for cellular antenna traces to 50 Ω.
5G Module Series RM505Q-AE Hardware Design 5.6. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S). Microstrip or coplanar waveguide is typically used in RF layout to control characteristic impedance.
5G Module Series RM505Q-AE Hardware Design Figure 33: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: ⚫ ⚫ ⚫ ⚫ ⚫ ⚫ Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
5G Module Series RM505Q-AE Hardware Design 5.7. Antenna Installation 5.7.1. Antenna Requirements The following table shows the requirements on WCDMA, LTE, 5G NR antenna and GNSS antenna.
5G Module Series RM505Q-AE Hardware Design Table 29: Major Specifications of the RF Connector Item Specification Nominal Frequency Range DC to 6 GHz Nominal Impedance 50 Ω Temperature Rating -40 °C to +85 °C Voltage Standing Wave Ratio (VSWR) Meet the requirements of: Max 1.3 (DC–3 GHz) Max 1.45 (3–6 GHz) The receptacle RF connector used in conjunction with RM505Q-AE will accept two types of mating plugs that will meet a maximum height of 1.2 mm using a Ø 0.
5G Module Series RM505Q-AE Hardware Design The following figure illustrates the connection between the receptacle RF connector on RM505Q-AE and the mating plug using a Ø 0.81 mm coaxial cable. Figure 36: Connection between RF Connector and Mating Plug Using Ø 0.81 mm Coaxial Cable The following figure illustrates the connection between the receptacle RF connector on RM505Q-AE and the mating plug using a Ø 1.13 mm coaxial cable. Figure 37: Connection between RF Connector and Mating Plug Using Ø 1.
5G Module Series RM505Q-AE Hardware Design 6 Reliability, Radio and Electrical Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 30: Absolute Maximum Ratings Parameter Min. Max. Unit VCC -0.3 4.7 V Voltage at Digital Pins -0.3 2.3 V 6.2. Power Supply Requirements The typical input voltage of RM505Q-AE is 3.7 V, as specified by PCIe M.
5G Module Series RM505Q-AE Hardware Design 6.3. I/O Requirements Table 32: I/O Requirements Parameter Description Min. Max. Unit VIH Input high voltage 0.7 × VDD18 1) VDD18 +0.3 V VIL Input low voltage -0.3 0.3 × VDD18 V VOH Output high voltage VDD18-0.5 VDD18 V VOL Output low voltage 0 0.4 V NOTE 1) V DD18 is the I/O power domain of the module. 6.4. Operating and Storage Temperatures Table 33: Operating and Storage Temperatures Parameter Min. Typ. Max.
5G Module Series RM505Q-AE Hardware Design call, etc., without any unrecoverable malfunction. Radio spectrum and radio network are not influenced, while one or more specifications, such as Pout, may undergo a reduction in value, exceeding the specified tolerances of 3GPP. When the temperature returns to the normal operating temperature level, the module will meet 3GPP specifications again. 6.5. Current Consumption Table 34: RM505Q-AE Current Consumption Description Conditions Typ.
5G Module Series RM505Q-AE Hardware Design transfer (GNSS OFF) LTE data transfer (GNSS OFF) WCDMA B1 HSUPA CH10700 @ 23 dBm TBD mA WCDMA B2 HSDPA CH9800 @ 23 dBm TBD mA WCDMA B2 HSUPA CH9800 @ 23 dBm TBD mA WCDMA B3 HSDPA CH1338 @ 23 dBm TBD mA WCDMA B3 HSUPA CH1338 @ 23 dBm TBD mA WCDMA B4 HSDPA CH1638 @ 23 dBm TBD mA WCDMA B4 HSUPA CH1638 @ 23 dBm TBD mA WCDMA B5 HSDPA CH4407 @ 23 dBm TBD mA WCDMA B5 HSUPA CH4407 @ 23 dBm TBD mA WCDMA B6 HSDPA CH4400 @ 23 dBm TBD mA WCDMA
5G Module Series RM505Q-AE Hardware Design 5G NR data transfer (GNSS OFF) LTE-FDD B17 CH5790 @ 23 dBm TBD mA LTE-FDD B18 CH5925 @ 23 dBm TBD mA LTE-FDD B19 CH6075 @ 23 dBm TBD mA LTE-FDD B20 CH6300 @ 23 dBm TBD mA LTE-FDD B25 CH8365 @ 23 dBm TBD mA LTE-FDD B26 CH8865 @ 23 dBm TBD mA LTE-FDD B28 CH9435 @ 23 dBm TBD mA LTE-FDD B30 CH9820 @ 23 dBm TBD mA LTE-TDD B34 CH36275 @ 23 dBm TBD mA LTE-TDD B38 CH38000 @ 23 dBm TBD mA LTE-TDD B39 CH38450 @ 23 dBm TBD mA LTE-TDD B40 CH3
5G Module Series RM505Q-AE Hardware Design 5G NR-TDD n78 CH652666 @ 23 dBm TBD mA 5G NR-TDD n79 CH695090 @ 23 dBm TBD mA 5G NR-TDD n79 CH713522 @ 23 dBm TBD mA 5G NR-TDD n79 CH731976 @ 23 dBm TBD mA 5G NR-FDD n1 CH423000 @ 23 dBm TBD mA 5G NR-FDD n1 CH428000 @ 23 dBm TBD mA 5G NR-FDD n1 CH433000 @ 23 dBm TBD mA 5G NR-FDD n2 CH387000 @ 23 dBm TBD mA 5G NR-FDD n2 CH392000 @ 23 dBm TBD mA 5G NR-FDD n2 CH397000 @ 23 dBm TBD mA 5G NR-FDD n3 CH362000 @ 23 dBm TBD mA 5G NR-FDD n3
5G Module Series RM505Q-AE Hardware Design WCDMA voice call 5G NR-FDD n20 CH161200 @ 23 dBm TBD mA 5G NR-FDD n20 CH163200 @ 23 dBm TBD mA 5G NR-FDD n25 CH387000 @ 23 dBm TBD mA 5G NR-FDD n25 CH392500 @ 23 dBm TBD mA 5G NR-FDD n25 CH398000 @ 23 dBm TBD mA 5G NR-FDD n28 CH152600 @ 23 dBm TBD mA 5G NR-FDD n28 CH156100 @ 23 dBm TBD mA 5G NR-FDD n28 CH159600 @ 23 dBm TBD mA 5G NR-TDD n38 CH515000 @ 23 dBm TBD mA 5G NR-TDD n38 CH519000 @ 23 dBm TBD mA 5G NR-TDD n38 CH523000 @ 23 dB
5G Module Series RM505Q-AE Hardware Design WCDMA B8 CH3012 @ 23 dBm TBD mA WCDMA B19 CH338 @ 23 dBm TBD mA 6.6. RF Output Power The following table shows the RF output power of RM505Q-AE module. Table 35: RF Output Power Mode Frequency Max. Min.
5G Module Series RM505Q-AE Hardware Design LTE WCDMA B2 TBD TBD TBD -104.7 dBm WCDMA B3 TBD TBD TBD -103.7 dBm WCDMA B4 TBD TBD TBD -106.7 dBm WCDMA B5 TBD TBD TBD -104.7 dBm WCDMA B8 TBD TBD TBD -103.7 dBm WCDMA B19 TBD TBD TBD -104.7 dBm LTE-FDD B1 (10 MHz) TBD TBD TBD -96.3 dBm LTE-FDD B2 (10 MHz) TBD TBD TBD -94.3 dBm LTE-FDD B3 (10 MHz) TBD TBD TBD -93.3 dBm LTE-FDD B4 (10 MHz) TBD TBD TBD -96.3 dBm LTE-FDD B5 (10 MHz) TBD TBD TBD -94.
5G Module Series RM505Q-AE Hardware Design 5G NR LTE-FDD B32 (10 MHz) TBD TBD TBD -95.3 dBm LTE-TDD B34 (10 MHz) TBD TBD TBD -96.3 dBm LTE-TDD B38 (10 MHz) TBD TBD TBD -96.3 dBm LTE-TDD B39 (10 MHz) TBD TBD TBD -96.3 dBm LTE-TDD B40 (10 MHz) TBD TBD TBD -96.3 dBm LTE-TDD B41 (10 MHz) TBD TBD TBD -94.
5G Module Series RM505Q-AE Hardware Design 5G NR-TDD n41 (20 MHz) (SCS: 30 kHz) TBD TBD TBD -92.0 dBm 5G NR-FDD n66 (20 MHz) (SCS: 15 kHz) TBD TBD TBD -93.5 dBm 5G NR-FDD n71 (10 MHz) (SCS: 15 kHz) TBD TBD TBD -94.0 dBm 5G NR-TDD n77 (20 MHz) (SCS: 30 kHz) TBD TBD TBD -92.9 dBm 5G NR-TDD n78 (20 MHz) (SCS: 30 kHz) TBD TBD TBD -92.9 dBm 5G NR-TDD n79 (40 MHz) (SCS: 30 kHz) TBD TBD TBD -89.
5G Module Series RM505Q-AE Hardware Design 6.9. Thermal Dissipation RM505Q-AE is designed to work over an extended temperature range. To achieve a maximum performance while working under extended temperatures or extreme conditions (such as with maximum power or data rate) for a long time, it is strongly recommended to add a thermal pad or other thermally conductive compounds between the module and the main PCB for thermal dissipation. The thermal dissipation area on the bottom (i.e.
5G Module Series RM505Q-AE Hardware Design between the heatsink and the module, and the heatsink should be designed with as many fins as possible to increase the heat dissipation area. NOTE If a conformal coating is necessary for the module, do NOT use any coating material that may chemically react with the PCB or shielding cover, and prevent the coating material from flowing into the module.
5G Module Series RM505Q-AE Hardware Design 7 Mechanical Dimensions and Packaging This chapter mainly describes mechanical dimensions and packaging specifications of RM505Q-AE module. All dimensions are measured in mm, and the tolerances are ±0.05 mm unless otherwise specified. 7.1.
5G Module Series RM505Q-AE Hardware Design 7.2. Top and Bottom Views of the Module TOP View BOTTOM View Figure 40: TOP & Bottom View of the Module NOTE Images above are for illustration purpose only and may differ from the actual module. For authentic appearance and label, please refer to the module received from Quectel. 7.3. M.2 Connector RM505Q-AE adopts a standard PCI Express M.2 connector which compiles with the directives and standards listed in document [5]. 7.4.
5G Module Series RM505Q-AE Hardware Design Figure 41: Tray Size (Unit: mm) Each tray contains 10 modules. The smallest package contains 100 modules. Tray packaging procedures are as below. 1. 2. 3. 4. 5. 6. Use 10 trays to package 100 modules at a time (tray size: 247 mm × 172 mm). Place an empty tray on the top of the 10-tray stack. Fix the stack with masking tape in “#” shape as shown in the following figure. Pack the stack with conductive bag, and then fix the bag with masking tape.
5G Module Series RM505Q-AE Hardware Design 8 Appendix References Table 38: Related Documents SN. Document Name Description [1] Quectel_PCIe_Card_EVB_User_Guide PCIe card EVB user guide [2] Quectel_RG50xQ&RM5xxQ_Series_AT_Commands_ Manual AT commands manual for RG50xQ and RM5xxQ [3] Quectel_RG50xQ&RM5xxQ_Series_GNSS_Application_ Note The GNSS application note for RG50xQ and RM5xxQ series [4] Quectel_RF_Layout_Application_Note RF layout application note [5] PCI Express M.
5G Module Series RM505Q-AE Hardware Design GNSS Global Navigation Satellite System GPS Global Positioning System GRFC Generic RF Control GSM Global System for Mobile Communications HPUE High Power User Equipment HSPA High Speed Packet Access HSUPA High Speed Uplink Packet Access kbps Kilo Bits Per Second LAA License-Assisted Access LED Light Emitting Diode LTE Long Term Evolution MBIM Mobile Broadband Interface Model Mbps Mega Bits Per Second ME Mobile Equipment MIMO Multiple-I
5G Module Series RM505Q-AE Hardware Design PPP Point-to-Point Protocol QMI Qualcomm MSM (Mobile Station Modems) Interface RC Root Complex RF Radio Frequency RFFE RF Front-End R/LHCP Right/Left Hand Circular Polarization Rx Receive SAR Specific Absorption Rate SCS Subcarrier Spacing SDR Software-Defined Radio SIMO Single-Input Multiple-Output SMS Short Message Service Tx Transmit UART Universal Asynchronous Receiver & Transmitter UL Uplink URC Unsolicited Result Code USB Uni
OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.
Antenna (1) The antenna must be installed such that 20 cm is maintained between the antenna and users, (2) The transmitter module may not be co-located with any other transmitter or antenna. In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product.
Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required.
Industry Canada Statement This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device. Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence.
Cet appareil est conçu uniquement pour les intégrateurs OEM dans les conditions suivantes: (Pour utilisation de dispositif module) 1) L'antenne doit être installée de telle sorte qu'une distance de 20 cm est respectée entre l'antenne et les utilisateurs, et 2) Le module émetteur peut ne pas être coïmplanté avec un autre émetteur ou antenne. Tant que les 2 conditions ci-dessus sont remplies, des essais supplémentaires sur l'émetteur ne seront pas nécessaires.
Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual.
