Product Info

5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 22 / 83
54
PCIE_WAKE_N
DO
PCIe wake up
Open drain
Active LOW
55
PCIE_REFCLK_P
AI,
AO
PCIe reference clock (+)
56
RFFE_CLK*
DO
Used for external MIPI IC
control
1.8 V power domain
57
GND
Ground
58
RFFE_DATA*
DO
Used for external MIPI IC
control
1.8 V power domain
59
LAA_TX_EN
DO
Notification from SDR to
WL when LTE transmitting
1.8 V power domain
60
WLAN_TX_EN
DI
Notification from WL to
SDR while transmitting
1.8 V power domain
61
ANTCTL1*
DO
Antenna control
1.8 V power domain
62
COEX_RXD
DI
LTE/WLAN coexistence
receive data
1.8 V power domain
63
ANTCTL2*
DO
Antenna control
1.8 V power domain
64
COEX_TXD
DO
LTE/WLAN coexistence
transmit data
1.8 V power domain
65
RFFE_VIO_1V8
PO
Power supply for RFFE
1.8 V power output
66
USIM_DET
DI
(U)SIM card insertion
detection
Internally pulled up to 1.8 V
67
RESET_N
DI
Reset the module.
Internally pulled up to 1.5 V
with a 100 kΩ resistor
Active LOW.
68
AP2SDX_STATUS
DI
Status indication from AP
1.8 V power domain
69
CONFIG_1
DO
Connected to GND
internally
70
VCC
PI
Power supply
V
min
= 3.135 V
V
norm
= 3.7 V
V
max
= 4.4 V
71
GND
Ground
72
VCC
PI
Power supply
Vmin = 3.135 V
Vnorm = 3.7 V
Vmax = 4.4 V
73
GND
Ground
74
VCC
PI
Power supply
Vmin = 3.135 V
Vnorm = 3.7 V