UG89 Hardware Design UMTS/HSPA+ Module Series Rev. UG89_Hardware_Design_V1.0 Date: 2020-07-12 Status: Preliminary www.quectel.
UMTS/HSPA+ Module Series UG89 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai, China 200233 Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
UMTS/HSPA+ Module Series UG89 Hardware Design About the Document History Revision Date Author Description 1.
UMTS/HSPA+ Module Series UG89 Hardware Design Contents About the Document .................................................................................................................................. 2 Contents ...................................................................................................................................................... 3 Table Index ..................................................................................................................................
UMTS/HSPA+ Module Series UG89 Hardware Design 4.1.2. Operating Frequency .................................................................................................... 44 4.1.3. Reference Design of RF Antenna Interface .................................................................. 45 4.1.4. Reference Design of RF Layout.................................................................................... 45 4.2. Antenna Installation ..................................................................
UMTS/HSPA+ Module Series UG89 Hardware Design Table Index Table 1: UG89 Frequency Bands ................................................................................................................. 9 Table 2: P/N Information ............................................................................................................................... 9 Table 3: Key Features of UG89 Module .....................................................................................................
UMTS/HSPA+ Module Series UG89 Hardware Design Figure Index Figure 1: Functional Diagram ..................................................................................................................... 13 Figure 2: Pin Assignment (Bottom View) ................................................................................................... 15 Figure 3: Voltage Drop during Burst Transmission ....................................................................................
UMTS/HSPA+ Module Series UG89 Hardware Design 1 Introduction This document defines UG89 module and describes its air interface and hardware interface which are connected with customers’ applications. This document helps customers quickly understand module interface specifications, electrical and mechanical details, as well as other related information of UG89 module. Associated with application note and user guide, customers can use UG89 module to design and set up mobile applications easily.
UMTS/HSPA+ Module Series UG89 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating UG89 module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product.
UMTS/HSPA+ Module Series UG89 Hardware Design 2 Product Concept 2.1. General Description UG89 is a WCDMA/GSM wireless communication module. Its general features are listed below： Support HSDPA, HSUPA, HSPA+, WCDMA, EDGE, GSM and GPRS coverage. Provide audio support for customers’ specific applications. Table 1: UG89 Frequency Bands Type Frequency Bands WCDMA B1/B2/B5/B6/B8 GSM 850/900/1800/1900MHz With a compact profile of 27.6mm × 25.4mm × 2.
UMTS/HSPA+ Module Series UG89 Hardware Design 2.2. Key Features The following table describes the detailed features of UG89 module. Table 3: Key Features of UG89 Module Feature Details Power Supply Supply voltage: 3.3V~4.5V Typical supply voltage: 3.
UMTS/HSPA+ Module Series UG89 Hardware Design PCM Interface USB Interface UART Interface Used for audio function with an external codec chip Support 16-bit linear data format Support short frame synchronization Support master and slave modes Compliant with USB 2.0 specification (slave only), with transmission rates up to 480Mbps Used for AT command communication, data transmission, software debugging and firmware upgrade Support USB serial drivers for: Windows 7/8/8.1/10 Windows CE 5.0/6.0/7.
UMTS/HSPA+ Module Series UG89 Hardware Design NOTES 1. 2. 1) Within the operation temperature range, the module is 3GPP compliant. the extended temperature range, the module remains the ability to establish and maintain a voice, SMS, data transmission, emergency call, etc. There is no unrecoverable malfunction. There are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce their value and exceed the specified tolerances.
UMTS/HSPA+ Module Series UG89 Hardware Design ANT_MAIN PAM Duplex VBAT_RF PA PRx Tx VBAT_BB 26M VC_TXCO Transceiver FLASH ADC IQ PMIC PWRKEY Control Control Baseband PON RAM 32K XO VDD_EXT VDD_EXT RESET_N I2C PCM UARTs USB (U)SIM GPIO STATUS Figure 1: Functional Diagram 2.4.
UMTS/HSPA+ Module Series UG89 Hardware Design 3 Application Interfaces 3.1. General Description UG89 is equipped with 120 pins that can be connected to customers’ cellular application platforms.
UMTS/HSPA+ Module Series UG89 Hardware Design 3.2. Pin Assignment GND 37 RESERVED 42 GND RESERVED 43 RESERVED UART1_DSR 44 38 UART1_DCD 45 39 UART1_DTR 46 GND USB_VBUS 47 RESERVED USB_DP 48 40 USB_DM 50 49 41 RESERVED RESERVED 52 51 STATUS GND 53 PWM2 54 The following figure shows the pin assignment of UG89 module.
UMTS/HSPA+ Module Series UG89 Hardware Design 3.3. Pin Description The following tables show the pin definition of UG89 module. Table 4: I/O Parameters Definition Type Description AI Analog Input AO Analog Output DI Digital Input DO Digital Output IO Bidirectional OD Open Drain PI Power Input PO Power Output Table 5: Pin Description Power Supply Pin Name VBAT VDD_EXT VCORE Pin No.
UMTS/HSPA+ Module Series UG89 Hardware Design If unused, keep it open. GND 3, 5, 8,37, 39, 41, 52, 58~62, 64~67, 73 82~84, 89~97, 106 110~120 Ground Turn On/Off Pin Name Pin No. I/O Description DC Characteristics Comment High pulse. Set this signal low before and after the startup impulse. PON 7 DI Turn on the module PWRKEY 79 DI Turn on/off the module VILmax=0.5V VBAT power domain. RESET_N 34 DI Reset the module Active Low. VILmax=0.5V If unused, keep it open.
UMTS/HSPA+ Module Series UG89 Hardware Design open. (U)SIM Interface Pin Name Pin No. I/O Description DC Characteristics Comment Iomax=50mA USIM_VDD 21 PO Power supply for (U)SIM card For 1.8V (U)SIM: Vmax=1.9V Vmin=1.7V For 3.0V (U)SIM: Vmax=3.05V Vmin=2.7V Either 1.8V or 3.0V (U)SIM card is supported and can be identified automatically by the module. For 1.8V (U)SIM: VILmax=0.6V VIHmin=1.2V VOLmax=0.45V VOHmin=1.35V USIM_DATA 18 IO (U)SIM card data For 3.0V (U)SIM: VILmax=1.0V VIHmin=1.
UMTS/HSPA+ Module Series UG89 Hardware Design UART1 Interface Pin Name UART1_RI UART1_DCD UART1_CTS UART1_RTS Pin No. 13 45 11 14 I/O Description DC Characteristics Comment DO Ring indicator VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. DO Data carrier detection VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. DO Clear to send from DTE VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open.
UMTS/HSPA+ Module Series UG89 Hardware Design VIHmin=1.2V VIHmax=2.0V open. 1.8V power domain. If unused, keep it open. Comment 33 DO Debug clear to send VOLmax=0.45V VOHmin=1.35V Pin Name Pin No. I/O Description DC Characteristics ANT_MAIN 63 IO Main antenna Pin No I/O Description DC Characteristics Comment 6 AI General purpose analog to digital converter interface Voltage range: 0V to 1.2 If unused, keep it open. Pin No.
UMTS/HSPA+ Module Series UG89 Hardware Design capacitor close to the pin. I2C Interface Pin Name I2C_SDA Pin No. 28 I/O OD Description DC Characteristics Comment I2C serial clock. Used for external codec An external 1.8V pull-up resistor is required. If unused, keep it open. An external 1.8V pull-up resistor is required. If unused, it is recommended to mount a 33pF capacitor close to the pin. 29 OD I2C serial data. Used for external codec Pin Name Pin No.
UMTS/HSPA+ Module Series UG89 Hardware Design NOTE COUNTER 56 DI Pulse Counter VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V I/O Description DC Characteristics 1.8V power domain. If unused, keep it open. Comment RESERVED Pins Pin Name Pin No. RESERVED 1, 2, 15, 38, 40, 42, 43, 50, 51, 68~71, 74~78, 80, 81, 85~88, 98~105, 107~109 Reserved Keep these pins unconnected. “*” means under development. 3.4.
UMTS/HSPA+ Module Series UG89 Hardware Design level. In this mode, the module can still receive paging message, SMS, voice call and TCP/UDP data from the network normally. Power Down Mode In this mode, the power management unit (PMU) shuts down the power supply, software goes inactive and the serial interfaces are not accessible. However, the VBAT pins are still powered. 3.5. Power Supply 3.5.1. Power Supply Pins UG89 provides two VBAT pins for connection with the external power supply.
UMTS/HSPA+ Module Series UG89 Hardware Design Burst Transmission Burst Transmission ≤2.0A Current VBAT <400mV Min. 3.3V Figure 3: Voltage Drop during Burst Transmission To decrease voltage drop, a bypass capacitor of about 100µF with low ESR (ESR≤0.7Ω) should be used, and a multi-layer ceramic chip (MLCC) capacitor array should also be reserved due to its ultra-low ESR.
UMTS/HSPA+ Module Series UG89 Hardware Design The following figure shows a reference design for a +5V input power source. The typical output of the power supply is about 3.8V and the maximum load current is 3.0A. MIC29302WU DC_IN VBAT OUT 5 3 1 51K 4 ADJ GND IN EN 2 100K 1% 470R 4.7K 470uF 100nF VBAT_EN 470uF 100nF 47K 1% 47K Figure 5: Reference Circuit of Power Supply 3.6. Power-on/off/Reset Scenarios 3.6.1.
UMTS/HSPA+ Module Series UG89 Hardware Design PWRKEY ≥ 500ms 4.7K 10nF Turn-on pulse 47K Figure 6: Reference Circuit of Turing on the Module Using Driving Circuit The other way to control the PWRKEY is using a button directly. When pressing the key, an electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure.
UMTS/HSPA+ Module Series UG89 Hardware Design NOTE 1 VBAT ≥500ms PWRKEY VIL≤0.5V About 5ms VDD_EXT ≥100ms. After this time, the pin can be set high level by an external circuit. USB_BOOT About 22ms RESET_N ≥10s STATUS (DO) ≥10s UART I nactive Active ≥10s USB Inactive Active Figure 8: Timing of Turning on the Module NOTES 1. 2. Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less than 30ms.
UMTS/HSPA+ Module Series UG89 Hardware Design 3.6.2.1. Turn off the Module Using the PWRKEY Pin Driving the PWRKEY pin to a low-level voltage for at least 650ms, the module will execute power-down procedure after the PWRKEY is released. The timing of turning off the module is illustrated in the following figure. VBAT ≥650ms ≥2s PWRKEY STATUS (DO) Module Status RUNNING Power-down procedure OFF Figure 9: Timing of Turning off the Module 3.6.2.2.
UMTS/HSPA+ Module Series UG89 Hardware Design possible and must be encircled by ground traces. Table 9: Pin Description of RESET_N Pin Name Pin No. I/O Description Comment RESET_N 34 DI Reset the module. Active low. 1.8V power domain. If unused, keep it open. The recommended circuit is similar to the PWRKEY control circuit. An open-drain/collector driver or button can be used to control the RESET_N. RESET_N 300ms 4.
UMTS/HSPA+ Module Series UG89 Hardware Design The timing of resetting module is illustrated in the following figure. VBAT 300ms RESET_N VIL Module Status Running 0.5V Baseband resetting Baseband restart Figure 12: Timing of Resetting Module NOTES 1. 2. 3. Please make sure that there is no large capacitance with the max value exceeding 10nF on PWRKEY and RESET_N pins. RESET_N only resets the internal baseband chip of the module and does not reset the power management chip.
UMTS/HSPA+ Module Series UG89 Hardware Design of UG89. After expiry of the 2 minute guard period, the presentation of URCs will be disabled, i.e. no URCs with alert levels "1" or ''-1" will be generated. URCs indicating the level "2" or "-2" are instantly followed by an orderly shutdown. The presentation of these URCs is always enabled, i.e. they will be output even though the factory setting AT+SCTM=0* was never changed. Please refer to document [2] for details about AT+SCTM* command.
UMTS/HSPA+ Module Series UG89 Hardware Design 3.6.4.3. Overvoltage Shutdown* The overvoltage shutdown threshold is the specified maximum supply voltage VBAT given in Table 23. When the average supply voltage measured by UG89 approaches the overvoltage shutdown threshold (i.e., 0.05V offset) the module will send the following URC: ^SBC: Overvoltage Warning The overvoltage warning is sent only once until the next time the module is close to the overvoltage shutdown threshold.
UMTS/HSPA+ Module Series UG89 Hardware Design UART1_CTS 11 DO DTE clear to send UART1_RTS 14 DI DTE request to send UART1_DTR 46 DI Data terminal ready UART1_TXD 10 DO Transmit data UART1_RXD 12 DI Receive data UART1_DSR 44 DO Data set ready Table 12: Pin Definition of the Debug UART Interface Pin Name Pin No.
UMTS/HSPA+ Module Series UG89 Hardware Design VDD_EXT VCCA 120K VCCB 10K 0.1uF VDD_MCU 0.1uF OE GND UART1_RI A1 B1 RI_MCU UART1_DCD A2 B2 DCD_MCU UART1_CTS A3 B3 CTS_MCU UART1_RTS A4 B4 RTS_MCU UART1_DTR A5 B5 DTR_MCU UART1_TXD A6 B6 TXD_MCU UART1_RXD A7 B7 RXD_MCU UART1_DSR A8 B8 DSR_MCU Translator Figure 13: Reference Circuit with a Level Translator Chip Please visit http://www.ti.com for more information.
UMTS/HSPA+ Module Series UG89 Hardware Design NOTE The transistor circuit solution is not suitable for applications with baud rates exceeding 460Kbps. 3.8. (U)SIM Interface The (U)SIM interface circuitry meets ETSI and IMT-2000 SIM interface requirements. Both 1.8V and 3.0V (U)SIM cards are supported. Table 14: Pin Definition of the (U)SIM Card Interface Pin Name USIM_DET Pin No. 17 I/O Description Comment DI (U)SIM card hot-plug detect 1.8V power domain. If unused, keep it open. Either 1.8V or 3.
UMTS/HSPA+ Module Series UG89 Hardware Design VDD_EXT USIM_VDD 51K 15K 100nF USIM_GND (U)SIM Card Connector USIM_VDD Module USIM_RST 0R USIM_CLK USIM_DET 0R USIM_DATA 0R VCC RST CLK 33pF GND VPP IO GND 33pF 33pF GND GND Figure 15: Reference Circuit of (U)SIM Interface with an 8-pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET unconnected.
UMTS/HSPA+ Module Series UG89 Hardware Design In order to offer good ESD protection, it is recommended to add a TVS diode array whose parasitic capacitance should not be more than 15pF. The 0Ω resistors should be added in series between the module and the (U)SIM card to facilitate debugging. The 33pF capacitors are used for filtering interference of GSM900MHz. Please note that the (U)SIM peripheral circuit should be close to the (U)SIM card connector.
UMTS/HSPA+ Module Series UG89 Hardware Design Test Points Minimize these stubs Module VDD R3 NM_0R R4 NM_0R MCU ESD Array USB_VBUS L1 USB_DM USB_DM USB_DP USB_DP Close to Module GND GND Figure 17: Reference Circuit of USB Application A common mode choke L1 is recommended to be added in series between the module and customer’s MCU in order to suppress EMI spurious transmission.
UMTS/HSPA+ Module Series UG89 Hardware Design Table 16: Pin Definition of the ADC Interfaces Pin Name Pin No. Description ADC 6 General-purpose analog to digital converter The following table describes the characteristic of the ADC function. Table 17: Characteristic of the ADC Parameter Min. ADC Voltage Range 0 ADC Resolution Typ. Max. Unit 1.2 V 12 bits NOTE It is recommended to use a resistor divider circuit for ADC application. 3.11.
UMTS/HSPA+ Module Series UG89 Hardware Design 125us P CM _CLK 1 2 255 256 P CM _S YNC MS B LS B MS B MS B LS B MS B P CM _DOUT P CM _DIN Figure 18: Primary Mode Timing The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio codec design. Table 18: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_DIN 26 DI PCM data input 1.8V power domain If unused, keep it open PCM_DOUT 24 DO PCM data output 1.
UMTS/HSPA+ Module Series UG89 Hardware Design external codec I2C_SDA 28 is required. If unused, it is recommended to mount a 33pF capacitor close to the pin. I2C serial data for an external codec OD An external 1.8V pull-up resistor is required. If unused, keep it open. Clock and mode can be configured by AT command, and the default configuration is short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC.
UMTS/HSPA+ Module Series UG89 Hardware Design Pin Name STATUS Pin No. 53 I/O Description Comment DO Indicate the module’s operation status The following figure shows different circuit designs of STATUS, and customers can choose either one according to the application demands. VBAT Module 2.2K STATUS 4.7K 47K Figure 20: Reference Circuits of STATUS NOTE The status pin cannot be used as an indication of module shutdown status when VBAT is removed. 3.13.
UMTS/HSPA+ Module Series UG89 Hardware Design Table 20: Behaviors of the UART1_RI State Response Idle UART1_RI keeps at a high level URC UART1_RI outputs 120ms low pulse when a new URC is returned The UART1_RI behavior can be changed via AT+QCFG="urc/ri/ring" *. Please refer to document [2] for details. NOTE “*” means under development.
UMTS/HSPA+ Module Series UG89 Hardware Design 4 Antenna Interface UG89 includes a GSM/UMTS antenna interface. The RF interface has a 50Ω impedance. 4.1. GSM/UMTS Antenna Interface 4.1.1. Pin Definition The pin definition of the RF antenna is shown below. Table 21: Pin Definition of RF Antenna Pin Name Pin No. I/O GND 61 Ground GND 62 Ground ANT_MAIN 63 GND 64 Ground GND 65 Ground IO Description RF antenna pad Comment 50Ω impedance 4.1.2.
UMTS/HSPA+ Module Series UG89 Hardware Design WCDMA B5 824~849 869~894 MHz WCDMA B6 830~840 875~885 MHz WCDMA B8 880~915 925~960 MHz 4.1.3. Reference Design of RF Antenna Interface A reference design of RF antenna interface is recommended as below. A π-type matching circuit should be reserved for better RF performance, and the π-type matching components (R1/C1/C2) should be placed as close to the antenna as possible. The capacitors are not mounted by default.
UMTS/HSPA+ Module Series UG89 Hardware Design .
UMTS/HSPA+ Module Series UG89 Hardware Design Figure 25: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pins, and should be fully connected to ground.
UMTS/HSPA+ Module Series UG89 Hardware Design 4.2. Antenna Installation 4.2.1. Antenna Requirements The following table shows the requirements on GSM/UMTS antenna. Table 23: Antenna Requirements Type Requirements VSWR: ≤ 2 Efficiency: > 30% Max input power: 50W Input impedance: 50Ω Cable insertion loss: < 1dB Cable insertion loss: < 1.5dB (DCS1800/PCS1900，UMTS1900/2100 ) GSM/UMTS 4.2.2.
UMTS/HSPA+ Module Series UG89 Hardware Design U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 27: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector Figure 28: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com.
UMTS/HSPA+ Module Series UG89 Hardware Design 5 Electrical, Reliability and Radio Characteristics 5.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 24: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT -0.3 6.0 V USB_VBUS -0.3 5.5 V Peak Current of VBAT 0 2 A Voltage at Digital Pins -0.3 2.
UMTS/HSPA+ Module Series UG89 Hardware Design 5.2. Power Supply Ratings Table 25: The Module Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT The actual input voltages must be kept between the minimum and maximum values. 3.3 3.8 4.5 V Voltage drop during burst transmission Maximum power control level on GSM850/EGSM900. 400 mV IVBAT Peak supply current (during each transmission slot) Maximum power control level on GSM850/EGSM900. 1.8 2.
UMTS/HSPA+ Module Series UG89 Hardware Design effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce their value and exceed the specified tolerances. When the temperature returns to the normal operating temperature levels, the module will meet 3GPP specifications again. 5.4.
UMTS/HSPA+ Module Series UG89 Hardware Design EDGE data transfer WCDMA data transfer DCS1800 2DL/3UL @28.77dBm 373.7 mA DCS1800 1DL/4UL @26.69dBm 393.5 mA EGSM900 4DL/1UL @27.23dBm 171.3 mA EGSM900 3DL/2UL @27.10dBm 269.9 mA EGSM900 2DL/3UL @24.96dBm 316.9 mA EGSM900 1DL/4UL @23.15dBm 359.4 mA DCS1800 4DL/1UL @26.62dBm 160.3 mA DCS1800 3DL/2UL @26.46dBm 246.8 mA DCS1800 2DL/3UL @24.40dBm 301.4 mA DCS1800 1DL/4UL @22.11dBm 352.9 mA WCDMA B1 HSDPA @23.64dBm 598.
UMTS/HSPA+ Module Series UG89 Hardware Design WCDMA B2 @23.78dBm 658.1 mA WCDMA B5 @ 23.68dBm 623.9 mA WCDMA B8 @ 23.96dBm 632.3 mA 5.5. RF Output Power The following table shows the RF output power of UG89 module. Table 28: RF Output Power Frequency Max. Min.
UMTS/HSPA+ Module Series UG89 Hardware Design GSM850 -109.5dBm NA NA -102.0dBm EGSM900 -109.5dBm NA NA -102.0dBm DCS1800 -108.5dBm NA NA -102.0dBm PCS1900 -108dBm NA NA -102.0dBm WCDMA B1 -109.5dBm NA NA -106.7dBm WCDMA B2 -109.5dBm NA NA -104.7dBm WCDMA B5 -110dBm NA NA -104.7dBm WCDMA B6 -111dBm NA NA -106.7dBm WCDMA B8 -110dBm NA NA -103.7dBm 5.7. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general.
UMTS/HSPA+ Module Series UG89 Hardware Design 6 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm). The tolerances for dimensions without tolerance values are ±0.05mm. 6.1.
UMTS/HSPA+ Module Series UG89 Hardware Design Figure 30: Module Bottom Dimensions (Top View) UG89_Hardware_Design 57 / 73
UMTS/HSPA+ Module Series UG89 Hardware Design 6.2. Recommended Footprint Design Figure 31: Recommended Footprint (Top View) NOTES 1. For easy maintenance of the module, please keep about 3mm between the module and other components in the host PCB. 2. All RESERVED pins should be kept open and MUST NOT be connected to ground.
UMTS/HSPA+ Module Series UG89 Hardware Design 6.3.
UMTS/HSPA+ Module Series UG89 Hardware Design NOTE These are renderings of UG89 module. For authentic dimension and appearance, please refer to the module that you receive from Quectel.
UMTS/HSPA+ Module Series UG89 Hardware Design 7 Storage, Manufacturing and Packaging 7.1. Storage UG89 is stored in the vacuum-sealed bag. It is rated at MSL 3 and its storage restrictions are shown as below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/<90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be: 3. Devices require baking before mounting, if any circumstance below occurs. 4.
UMTS/HSPA+ Module Series UG89 Hardware Design 7.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.13mm~0.15mm. For more details, please refer to document [4].
UMTS/HSPA+ Module Series UG89 Hardware Design Soak time (between A and B: 150°C and 200°C) 60 to 120 sec Reflow Zone Max slope 2 to 3°C/sec Reflow time (D: over 220°C) 40 to 60 sec Max temperature 238°C ~ 245°C Cooling down slope 1 to 4°C/sec Reflow Cycle Max reflow cycle 1 NOTES 1.
UMTS/HSPA+ Module Series UG89 Hardware Design 8 Appendix A References Table 32: Related Documents SN Document Name Remark [1] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide [2] Quectel_UG89_AT_Commands_Manual UG89 AT Commands Manual [3] Quectel_RF_Layout_Application_Note RF Layout Application Note [4] Quectel_UMTS<E_EVB_User_Guide UMTS<E EVB user guide for UMTS<E modules Table 33: Terms and Abbreviations Abbreviation Description ADC Analog-to-Digital Conve
UMTS/HSPA+ Module Series UG89 Hardware Design ESD Electrostatic Discharge ESR Equivalent Series Resistance FDD Frequency Division Duplex FR Full Rate FTP File Transfer Protocol FTPS FTP-over-SSL GMSK Gaussian Minimum Shift Keying GSM Global System for Mobile Communications HR Half Rate HSPA High Speed Packet Access HSDPA High Speed Downlink Packet Access HSUPA High Speed Uplink Packet Access HTTP Hypertext Transfer Protocol LED Light Emitting Diode ME Mobile Equipment LTE Lon
UMTS/HSPA+ Module Series UG89 Hardware Design PPP Point-to-Point Protocol PSK Phase Shift Keying QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency SMS Short Message Service SMTP Simple Mail Transfer Protocol SSL Secure Sockets Layer TCP Transmission Control Protocol TDD Time Division Duplexing UART Universal Asynchronous Receiver &Transmitter UDP User Datagram Protocol UL Uplink UMTS Universal Mobile Telecommunications System URC Unsolici
UMTS/HSPA+ Module Series UG89 Hardware Design VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VSWR Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access WLAN Wireless Local Area Network UG89_Hardware_Design 67 / 73
UMTS/HSPA+ Module Series UG89 Hardware Design 9 Appendix B GPRS Coding Schemes Table 34: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
UMTS/HSPA+ Module Series UG89 Hardware Design 10 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
UMTS/HSPA+ Module Series UG89 Hardware Design 13 3 3 NA 14 4 4 NA 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 UG89_Hardware_Design 70 / 73
UMTS/HSPA+ Module Series UG89 Hardware Design 11 Appendix D EDGE Modulation and Coding Schemes Table 36: EDGE Modulation and Coding Schemes Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1: GMSK / 9.05kbps 18.1kbps 36.2kbps CS-2: GMSK / 13.4kbps 26.8kbps 53.6kbps CS-3: GMSK / 15.6kbps 31.2kbps 62.4kbps CS-4: GMSK / 21.4kbps 42.8kbps 85.6kbps MCS-1 GMSK C 8.80kbps 17.60kbps 35.20kbps MCS-2 GMSK B 11.2kbps 22.4kbps 44.
UMTS/HSPA+ Module Series UG89 Hardware Design 12 Appendix E Certification List Table 37: Certification List Country or Operator Comment Australia Government RCM 2 months Australia Telstra 4 months(need RCM & GCF) Australia Vodafone 3 months(need FCC & PTCRB) Brazil Government ANATEL 5 months Brazil Vivo Modules do not need to do Vivo certification.
UMTS/HSPA+ Module Series UG89 Hardware Design UK Vodafone 3 months(need CE & GCF) USA FCC/IC/PTCRB/UL Gov. FCC/IC: 2 months PTCRB: 3 months UL: Modules do not need to do UL. USA AT&T 5~6 Months(need FCC & PTCRB).
FCC KDB996369 D03v01 Requirements List of applicable FCC rules FCC Part 15 Subpart B, Part 22 Subpart H, Part 24 Subpart E Summarize the specific operational use conditions Not Applicable Limited module procedures Not Applicable Trace antenna designs Refer to Manual Section 4 RF exposure considerations Refer to FCC certification requirements Antennas Technology Frequency Range Antenna Type Max Peak Gain (dBi) (MHz) GSM850 824.2 ~ 848.8 PCS1900 1850.2 ~ 1909.8 WCDMA Band II 1852.4 ~ 1907.
FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met: 1. This Modular Approval is limited to OEM installation for mobile and fixed applications only.
provided the user can reasonably be expected to have the capability to access information in that form. This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the user's authority to operate the equipment.
Antennas Technology Frequency Range Antenna Type Max Peak Gain (dBi) (MHz) GSM850 824.2 ~ 848.8 PCS1900 1850.2 ~ 1909.8 WCDMA Band II 1852.4 ~ 1907.6 WCDMA Band V 826.4 ~ 846.6 2.29 Dipole 1.59 1.59 2.29 Antennes Technologie Gamme de Type d'antenne Gain de crête fréquences (MHz) maximum (dBi) GSM850 824.2 ~ 848.8 2.29 PCS1900 1850.2 ~ 1909.8 WCDMA Bande II 1852.4 ~ 1907.6 WCDMA Bande V 826.4 ~ 846.6 Dipôle 1.59 1.59 2.
