Product Info

LPWA Module Series
BG600L-M3 Hardware Design
BG600L-M3_Hardware_Design 44 / 83
AT+IPR command can be used to set the baud rate of the main UART interface, and AT+IFC command
can be used to enable/disable hardware flow control (hardware flow control is disabled by default). Please
refer to document [2] for more details about these AT commands.
Table 13: Pin Definition of Debug UART Interface
Table 14: Pin Definition of GNSS UART Interface
The logic levels of UART interfaces are described in the following table.
Table 15: Logic Levels of Digital I/O
The module provides 1.8 V UART interfaces. A voltage-level translator should be used if customers’
application is equipped with a 3.3 V UART interface. The voltage-level translator TXS0108EPWR
provided by Texas Instruments is recommended, and please visit http://www.ti.com for more information.
MAIN_RI 35 DO Main UART ring indication 1.8 V power domain
Pin Name Pin No. I/O Description Comment
DBG _TXD 29 DO Debug UART transmit 1.8 V power domain
DBG _RXD 30 DI Debug UART receive 1.8 V power domain
Pin Name Pin No. I/O Description Comment
GNSS_ TXD 22 DO GNSS UART transmit 1.8 V power domain
GNSS_ RXD 23 DI GNSS UART receive 1.8 V power domain
Parameter Min. Max. Unit
V
IL
-0.3 0.6 V
V
IH
1.2 2.0 V
V
OL
0 0.45 V
V
OH
1.35 1.8 V
NOTE