BG600L-M3 Hardware Design LPWA Module Series Rev. BG600L-M3_Hardware_Design_V1.0 Date: 2020-03-30 Status: Released www.quectel.
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LPWA Module Series BG600L-M3 Hardware Design About the Document Revision History Version Date Author Description 1.
LPWA Module Series BG600L-M3 Hardware Design Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index .................................................................................................................................
LPWA Module Series BG600L-M3 Hardware Design 3.17. ADC Interface............................................................................................................................ 50 3.18. GPIO Interfaces* ....................................................................................................................... 51 3.19. GRFC Interfaces* ...................................................................................................................... 52 4 GNSS Receiver ...........
LPWA Module Series BG600L-M3 Hardware Design Table Index Table 1: Frequency Bands and GNSS Types of BG600L-M3 Module ...................................................... 14 Table 2: Key Features of BG600L-M3 Module .......................................................................................... 15 Table 3: Definition of I/O Parameters......................................................................................................... 21 Table 4: Pin Description .............................
LPWA Module Series BG600L-M3 Hardware Design Table 42: Electrostatic Discharge Characteristics (25 ºC, 45% Relative Humidity) .................................. 71 Table 43: Recommended Thermal Profile Parameters ............................................................................. 78 Table 44: Module Packaging Specifications .............................................................................................. 80 Table 45: Related Documents..................................................
LPWA Module Series BG600L-M3 Hardware Design Figure Index Figure 1: Functional Diagram ..................................................................................................................... 18 Figure 2: Pin Assignment (Top View) ........................................................................................................ 20 Figure 3: Sleep Mode Application via UART .............................................................................................
LPWA Module Series BG600L-M3 Hardware Design 1 Introduction This document defines BG600L-M3 module and describes its air interface and hardware interfaces which are connected with customers’ applications. This document helps customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of BG600L-M3. To facilitate application designs, it also includes some reference designs for customers’ reference.
LPWA Module Series BG600L-M3 Hardware Design 1.1 Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating BG600L-M3 module. Manufacturers of the cellular terminal should notify users and operating personnel of the following safety information by incorporating these guidelines into all manuals of the product.
LPWA Module Series BG600L-M3 Hardware Design 1.2 CE Certificate Requirement CE Statement The minimum distance between the user and/or any bystander and the radiating structure of the transmitter is 20cm. Hereby, We, Quectel Wireless Solutions Co., Ltd. declares that the radio equipment type BG600L-M3 is in compliance with the Directive 2014/53/EU. The full text of the EU declaration of conformity is available at the following internet address: Building 5, Shanghai Business Park Phase III (Area B), No.
LPWA Module Series BG600L-M3 Hardware Design ❒ NB LTE Band4/66:≤8.000dBi ❒ NB LTE Band5:≤12.541 dBi ❒ NB LTE Band12:≤11.798dBi ❒ NB LTE Band13:≤12.214dBi ❒ NB LTE Band71:≤11.687dBi ❒NB LTE Band85:≤11.798 dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines.
LPWA Module Series BG600L-M3 Hardware Design 1.4 IC Statement IRSS-GEN "This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." or "Le présent appareil est conforme aux CNR d’Industrie Canada applicables aux appareils radio exempts de licence.
LPWA Module Series BG600L-M3 Hardware Design L'étiquette de certification d'Innovation, Sciences et Développement économique Canada d'un module doit être clairement visible en tout temps lorsqu'il est installédans le produit hôte; sinon, le produit hôte doit porter une étiquette indiquant le numéro de certification d'Innovation, Sciences et Développement économique Canada pour le module, précédé du mot «Contient» ou d'un libellé semblable exprimant la même signification, comme suit:"Contient IC: 10224A-20B
LPWA Module Series BG600L-M3 Hardware Design 2 Product Concept 2.1 General Description BG600L-M3 is an embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless communication module. It provides data connectivity on LTE-FDD and GPRS/EGPRS networks, and supports half-duplex operation in LTE network. It also provides GNSS and voice* 1) functionality to meet customers’ specific application demands.
LPWA Module Series BG600L-M3 Hardware Design 1.5 Key Features The following table describes the detailed features of BG600L-M3 module. Table 2: Key Features of BG600L-M3 Module Features Details Power Supply Supply voltage: 3.3–4.3 V Typical supply voltage: 3.8 V Transmitting Power Class 5 (21 dBm + 1.
LPWA Module Series BG600L-M3 Hardware Design Point to point MO and MT SMS cell broadcast SMS storage: ME by default (U)SIM Interface Support 1.8 V USIM/SIM card only PCM Interface* Support one digital audio interface: PCM interface USB Interface Compliant with USB 2.
LPWA Module Series BG600L-M3 Hardware Design 1. 2. 1) Within operation temperature range, the module meets 3GPP specifications. Within the extended temperature range, the module remains the ability to establish and maintain functions such as voice, SMS, data transmission, emergency call, etc., without any unrecoverable malfunction.
LPWA Module Series BG600L-M3 Hardware Design Figure 1: Functional Diagram NOTES 1. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY should never be pulled down to GND permanently. 2. RESET_N is connected directly to PWRKEY inside the module. 1.
LPWA Module Series BG600L-M3 Hardware Design 2 Application Interfaces BG600L-M3 is equipped with 68 LGA pads that can be connected to customers’ cellular application platforms.
LPWA Module Series BG600L-M3 Hardware Design 2.
LPWA Module Series BG600L-M3 Hardware Design NOTES 1. 2. 3. 4. 5. 6. 7. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY should never be pulled down to GND permanently. RESET_N is connected directly to PWRKEY inside the module. ADC input voltage must not exceed 1.8 V. The input voltage range of USB_VBUS is 1.3–1.8 V.
LPWA Module Series BG600L-M3 Hardware Design Table 4: Pin Description Power Supply Pin Name Pin No. I/O Description DC Characteristics Vmax = 4.3 V Vmin = 3.3 V Vnorm = 3.8 V Comment VBAT_BB 51 PI Power supply for the module’s baseband part VBAT_RF 50 PI Power supply for the module’s RF part Vmax = 4.3 V Vmin = 3.3 V Vnorm = 3.8 V PO 1.8 V output power supply for external circuits Vnorm = 1.8 V IOmax = 50 mA If unused, keep this pin open.
LPWA Module Series BG600L-M3 Hardware Design pin open. USB Interface Pin Name Pin No. I/O Description DC Characteristics USB_VBUS 32 AI USB connection detect VIHmax = 1.8 V VIHmin = 1.3 V Comment Compliant with USB 2.0 standard specification. Require differential impedance of 90 Ω. USB_DP 24 IO USB differential data (+) USB_DM 25 IO USB differential data (-) USBPHY_3P3 17 PI Power supply for USB PHY circuit Vnorm = 3.3 V 8 DO External LDO enable control for USB VOLmax = 0.
LPWA Module Series BG600L-M3 Hardware Design VIHmax = 2.0 V MAIN_RXD 34 DI Main UART receive VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep this pin open. 1.8 V power domain. If unused, keep this pin open. MAIN_TXD 33 DO Main UART transmit VOLmax = 0.45 V VOHmin = 1.35 V MAIN_CTS 38 DO Main UART clear to send VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. If unused, keep this pin open. DI Main UART request to send VILmin = -0.
LPWA Module Series BG600L-M3 Hardware Design PCM Interface* Pin Name PCM_CLK PCM_SYNC PCM_DIN PCM_DOUT Pin No. 59 61 62 I/O Description DC Characteristics Comment DO PCM clock VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. If unused, keep this pin open. DO PCM data frame sync VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. If unused, keep this pin open. PCM data input VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain.
LPWA Module Series BG600L-M3 Hardware Design input/output GPIO2 GPIO3 GPIO4 GPIO5 10 11 12 53 IO IO IO IO VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V Do not pull it up before startup. 1.8 V power domain. If unused, keep this pin open. General-purpose input/output VOLmax = 0.45 V VOHmin = 1.35 V VILmin = -0.3 V VILmax = 0.6 V VIHmin = 1.2 V VIHmax = 2.0 V 1.8 V power domain. If unused, keep this pin open. General-purpose input/output VOLmax = 0.
LPWA Module Series BG600L-M3 Hardware Design GRFC1 GRFC2 63 64 DO Generic RF controller VOLmax = 0.45 V VOHmin = 1.35 V BOOT_CONFIG. Do not pull it up before startup. 1.8 V power domain. If unused, keep this pin open. DO Generic RF controller VOLmax = 0.45 V VOHmin = 1.35 V 1.8 V power domain. If unused, keep this pin open. I/O Description DC Characteristics Comment PON_TRIG Interface Pin Name PON_TRIG Pin No. 1.8 V power domain. Rising-edge triggered. If unused, keep this pin open.
LPWA Module Series BG600L-M3 Hardware Design 2. 3. 4. 5. 6. 7. should never be pulled down to GND permanently. RESET_N is connected directly to PWRKEY inside the module. The input voltage range of USB_VBUS is 1.3–1.8 V. GPIO1 (pin 9), NET_STATUS (pin 47), GRFC1 (pin 63) and GNSS_LNA_EN (pin 66) are BOOT_CONFIG pins, and please do not pull them up before startup. USBPHY_3P3 and USBPHY_3P3_EN pins are used for USB PHY circuits. Keep all RESERVED pins and unused pins unconnected. “*” means under development.
LPWA Module Series BG600L-M3 Hardware Design NOTE During e-I-DRX, it is recommended to use UART interface for data communication, as the use of USB interface will increase power consumption. 2.4 Power Saving 2.4.1 Airplane Mode When the module enters airplane mode, the RF function does not work, and all AT commands correlative with RF function will be inaccessible. The module can be set into Airplane mode through AT+CFUN=.
LPWA Module Series BG600L-M3 Hardware Design Drive PWRKEY low will wake up the module. When the T3412_Ext timer expires, the module will be woken up automatically. NOTE Please refer to document [2] for details about AT+CPSMS command. 2.4.
LPWA Module Series BG600L-M3 Hardware Design Execute AT+QSCLK=1 command to enable sleep mode. Drive MAIN_DTR pin high. The following figure shows the connection between the module and the host. Figure 3: Sleep Mode Application via UART When BG600L-M3 has URC to report, MAIN_RI signal will wake up the host. Please refer to Chapter 3.15 for details about MAIN_RI behavior. Driving the MAIN_DTR of host low will wake up the module. 2.5 Power Supply 2.5.
LPWA Module Series BG600L-M3 Hardware Design GND 14, 16, 27, 31, 40, 42, 44, 45, 48, 49 Ground - - - - 2.5.2 Decrease Voltage Drop The power supply range of the BG600L-M3 is 3.3–4.3 V. Please make sure that the input voltage will never drop below 3.3 V. The following figure shows the voltage drop during burst transmission in 2G network of BG600L-M3 module. The voltage drop will be less in LTE Cat M1 and/or LTE Cat NB2 networks.
LPWA Module Series BG600L-M3 Hardware Design Figure 5: Star Structure of the Power Supply 2.5.3 Monitor the Power Supply AT+CBC command can be used to monitor the VBAT_BB voltage value. For more details, please refer to document [2]. 2.6 Turn on and off Scenarios 2.6.1 Turn on Module with PWRKEY The following table shows the pin definition of PWRKEY. Table 7: Pin Definition of PWRKEY Pin Name PWRKEY Pin No. 5 Description DC Characteristics Comment Turn on/off the module Vnorm = 1.5 V VILmax = 0.
LPWA Module Series BG600L-M3 Hardware Design Figure 6: Turn on the Module Using Driving Circuit Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection. A reference circuit is shown in the following figure.
LPWA Module Series BG600L-M3 Hardware Design The power on scenario is illustrated in the following figure. Figure 8: Power-on Timing NOTES 1. Make sure that VBAT is stable before pulling down PWRKEY pin and keep the interval no less than 30 ms. 2. PWRKEY output voltage is 1.5 V because of the voltage drop inside the Qualcomm chipset. Due to platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY should never be pulled down to GND permanently. 2.6.
LPWA Module Series BG600L-M3 Hardware Design 2.6.2.1 Turn off Module with PWRKEY Driving PWRKEY low for 650–1500 ms, the module will execute power-down procedure after PWRKEY is released. The power-off scenario is illustrated in the following figure. Figure 9: Power-off Timing 2.6.2.2 Turn off Module with AT Command It is also a safe way to use AT+QPOWD command to turn off the module, which is similar to turning off the module with PWRKEY. Please refer to document [2] for details about AT+QPOWD command.
LPWA Module Series BG600L-M3 Hardware Design Table 8: Pin Definition of RESET_N Pin Name RESET_N Pin No. 4 Description Reset the module DC Characteristics Comment VILmax = 0.45 V Multiplexed from PWRKEY (connected directly to PWRKEY inside the module). The reset scenario is illustrated in the following figure. VBA T ≤ 3.8 s ≥2s RESET_N V IL ≤ 0.45 V Module Status Running Resetting Restart Figure 10: Reset Timing The recommended circuit is similar to the PWRKEY control circuit.
LPWA Module Series BG600L-M3 Hardware Design S2 RESET_N TVS Close to S2 Figure 12: Reference Circuit of RESET_N by Using Button NOTE Please assure that there is no large capacitance on RESET_N pin. 2.8 PON_TRIG Interface BG600L-M3 module provides one PON_TRIG pin, which is used to wake up the module from PSM. When the pin detects a rising edge, the module will be woken up from PSM. Table 9: Pin Definition of PON_TRIG Interface Pin Name PON_TRIG Pin No.
LPWA Module Series BG600L-M3 Hardware Design VDD_1V8 10K 10K PON_TRIG_EXT 100K 100K PON_TRIG Figure 13: Reference Design of PON_TRIG NOTE VDD_1V8 is provided by an external LDO. 2.9 (U)SIM Interface BG600L-M3 supports 1.8 V (U)SIM card only. The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Table 10: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment USIM_DET* 26 DI (U)SIM card hot-plug detect 1.8 V power domain.
LPWA Module Series BG600L-M3 Hardware Design The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector. Figure 14: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_DET unconnected. A reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure.
LPWA Module Series BG600L-M3 Hardware Design Keep (U)SIM card signals away from RF and VBAT traces. Assure the ground trace between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5 mm to maintain the same electric potential. To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and shield them with surrounded ground. USIM_RST should also be surrounded with ground.
LPWA Module Series BG600L-M3 Hardware Design The USB interface is recommended to be reserved for firmware upgrade or debugging in application designs. The following figures illustrate reference designs of USB PHY and USB interface. U1 VBAT C1 1 μF VDD_EXT USBPHY_3P3_EN R1 10K R2 0R VIN VOUT EN GND SG M2040-3.
LPWA Module Series BG600L-M3 Hardware Design Junction capacitance of the ESD protection device might cause influences on USB data lines, so please pay attention to the selection of the device. Typically, the stray capacitance should be less than 2 pF. Keep the ESD protection devices as close to the USB connector as possible. NOTES 1. BG600L-M3 can only be used as a slave device. 2. The input voltage range of USB_VBUS is 1.3–1.8 V. 2.
LPWA Module Series BG600L-M3 Hardware Design MAIN_RI 35 DO Main UART ring indication 1.8 V power domain NOTE AT+IPR command can be used to set the baud rate of the main UART interface, and AT+IFC command can be used to enable/disable hardware flow control (hardware flow control is disabled by default). Please refer to document [2] for more details about these AT commands. Table 13: Pin Definition of Debug UART Interface Pin Name Pin No.
LPWA Module Series BG600L-M3 Hardware Design The following figure shows a reference design of the main UART interface: Figure 18: Main UART Reference Design (Translator Chip) Another example with transistor translation circuit is shown as below. For the design of circuits in dotted lines, please refer to that of circuits in solid lines, but please pay attention to the direction of connection.
LPWA Module Series BG600L-M3 Hardware Design 2.12 PCM and I2C Interfaces* BG600L-M3 provides one Pulse Code Modulation (PCM) digital interface and one I2C interface. The following table shows the pin definition of the two interfaces which can be applied on audio codec design. Table 16: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_CLK 59 DO PCM clock 1.8 V power domain PCM_SYNC 61 DO PCM data frame sync 1.
LPWA Module Series BG600L-M3 Hardware Design 2.13 Network Status Indication BG600L-M3 provides one network status indication pin: NET_STATUS. The pin is used to drive a network status indication LED. The following tables describe the pin definition and logic level changes of NET_STATUS in different network activity status. Table 17: Pin Definition of NET_STATUS Pin Name NET_STATUS Pin No. 47 I/O Description Comment DO Indicate the module’s network activity status BOOT_CONFIG.
LPWA Module Series BG600L-M3 Hardware Design 2.14 STATUS The STATUS pin is used to indicate the operation status of BG600L-M3 module. It will output high level when the module is powered on. The following table describes the pin definition of STATUS. Table 19: Pin Definition of STATUS Pin Name STATUS Pin No. 13 I/O Description Comment DO Indicate the module’s operation status 1.8 V power domain The following figure shows a reference circuit of STATUS. Figure 22: Reference Design of STATUS 2.
LPWA Module Series BG600L-M3 Hardware Design URC MAIN_RI outputs 120 ms low pulse when a new URC returns. The default MAIN_RI behaviors can be configured flexibly by AT+QCFG="urc/ri/ring" command. For more details about AT+QCFG, please refer to document [2]. NOTE URC can be outputted from UART port, USB AT port and USB modem port, through configuration via AT+QURCCFG command. The default port is USB AT port. 2.16 USB_BOOT Interface BG600L-M3 provides a USB_BOOT pin.
LPWA Module Series BG600L-M3 Hardware Design The following figure shows the timing of USB_BOOT. NOTE VBAT 500–1000 ms PWRKEY VIL ≤ 0.45 V About 30 ms VDD_EXT Pulling up USB_BOOT to 1.8 V before VDD_EXT powerup will force the module into emergency download mode after the module is powered on. USB_BOOT Figure 24: Timing of Turning on Module with USB_BOOT NOTES 1. It is recommended to reserve the above circuit design during application design. 2.
LPWA Module Series BG600L-M3 Hardware Design Table 22: Pin Definition of ADC Interface Pin Name Pin No. I/O Description Comment ADC 6 AI General-purpose ADC interface Voltage range: 0.1–1.8 V The following table describes the characteristics of ADC interface. Table 23: Characteristics of ADC Interface Parameter Min. Voltage Range 0.1 Typ. Max. Unit 1.8 V Resolution (LSB) 64.979 μV Analog Bandwidth 500 kHz Sample Clock 4.8 MHz Input Resistance 10 MΩ NOTES 1.
LPWA Module Series BG600L-M3 Hardware Design GPIO2 10 IO General-purpose input/output GPIO3 11 IO General-purpose input/output GPIO4 12 IO General-purpose input/output GPIO5 53 IO General-purpose input/output GPIO6 54 IO General-purpose input/output The following table describes the characteristics of GPIO interfaces. Table 25: Logic Levels of GPIO Interfaces Parameter Min. Max. Unit VIL -0.3 0.6 V VIH 1.2 2.0 V VOL 0 0.45 V VOH 1.35 1.8 V NOTES 1.
LPWA Module Series BG600L-M3 Hardware Design Table 27: Logic Levels of GRFC Interfaces Parameter Min. Max. Unit VOL 0 0.45 V VOH 1.35 1.8 V Table 28: Truth Table of GRFC Interfaces GRFC1 Level GRFC2 Level Frequency Range (MHz) Band Low Low 880–2200 B1, B2, B3, B4, B8, B25, B66 High Low 791–894 B5, B18, B19, B20, B26, B27 Low High 698–803 B12, B13, B14, B28, B85 High High 617–698 B71 NOTES 1. GRFC1 is a BOOT_CONFIG pin, and please do not pull it up before startup. 2.
LPWA Module Series BG600L-M3 Hardware Design 3 GNSS Receiver 3.1 General Description BG600L-M3 includes a fully integrated global navigation satellite system solution that supports Gen9 VT of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). The module supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1 Hz data update rate via USB interface by default. By default, BG600L-M3 GNSS engine is switched off. It has to be switched on via AT command.
LPWA Module Series BG600L-M3 Hardware Design Accuracy (GNSS) @ open sky XTRA enabled TBD s CEP-50 Autonomous @ open sky TBD m NOTES 1. 2. 3. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep positioning for at least 3 minutes continuously). Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock within 3 minutes after loss of lock.
LPWA Module Series BG600L-M3 Hardware Design 4 Antenna Interfaces BG600L-M3 includes a main antenna interface and a GNSS antenna interface. The antenna ports have an impedance of 50 Ω. 4.1 Main Antenna Interface 4.1.1 Pin Definition The pin definition of main antenna interface is shown below. Table 30: Pin Definition of Main Antenna Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 41 IO Main antenna interface 50 Ω characteristic impedance 4.1.
LPWA Module Series BG600L-M3 Hardware Design LTE-FDD B13 777–787 746–756 MHz LTE-FDD B14 1) 788–798 758–768 MHz LTE-FDD B18 815–830 860–875 MHz LTE-FDD B19 830–845 875–890 MHz LTE-FDD B20 832–862 791–821 MHz LTE-FDD B25 1850–1915 1930–1995 MHz LTE-FDD B26 814–849 859–894 MHz LTE-FDD B27 1) 807–824 852–869 MHz LTE-FDD B28 703–748 758–803 MHz LTE-FDD B66 1710–1780 2110–2180 MHz LTE-FDD B71 2) 663–698 617–652 MHz LTE-FDD B85 698–716 728–746 MHz NOTES 1. 2.
LPWA Module Series BG600L-M3 Hardware Design Figure 25: Reference Design of Main Antenna Interface 4.1.4 Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50 Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the height from the reference ground to the signal layer (H), and the spacing between RF traces and grounds (S).
LPWA Module Series BG600L-M3 Hardware Design Figure 27: Coplanar Waveguide Design on a 2-layer PCB Figure 28: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 29: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) BG600L-M3_Hardware_Design 59 / 83
LPWA Module Series BG600L-M3 Hardware Design In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50 Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
LPWA Module Series BG600L-M3 Hardware Design A reference design of GNSS antenna interface is shown as below. Figure 30: Reference Design of GNSS Antenna Interface NOTES 1. 2. An external LDO can be selected to supply power according to the active antenna requirement. If the module is designed with a passive antenna, then the VDD circuit is not needed. 4.3 Antenna Installation 4.3.1 Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna.
LPWA Module Series BG600L-M3 Hardware Design Max Input Power: 50 W Input Impedance: 50 Ω Cable Insertion Loss: < 1 dB (LTE B5/B8/B12/B13/B14/B18/B19/B20/B26/B27/B28/B71/B85, GSM850/EGSM900) Cable Insertion Loss: < 1.5 dB (LTE B1/B2/B3/B4/B25/B66, DCS1800/PCS1900) NOTE 1) It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of active antenna may generate harmonics which will affect the GNSS performance. 4.3.
LPWA Module Series BG600L-M3 Hardware Design U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 32: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector. Figure 33: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com.
LPWA Module Series BG600L-M3 Hardware Design 5 Electrical, Reliability and Radio Characteristics 5.1 Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 35: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_BB -0.5 6.0 V VBAT_RF -0.3 6.0 V USB_VBUS 1.3 1.8 V Voltage at Digital Pins -0.3 2.09 V 5.
LPWA Module Series BG600L-M3 Hardware Design USB_VBUS USB detection 1.3 1.8 V 5.3 Operation and Storage Temperatures The operation and storage temperatures of the module are listed in the following table. Table 37: Operation and Storage Temperatures Parameter Min. Typ. Max. Unit Operation Temperature Range 1) -35 +25 +75 ºC Extended Temperature Range 2) -40 +85 ºC Storage Temperature Range -40 +90 ºC NOTES 1. 2.
LPWA Module Series BG600L-M3 Hardware Design Rock Bottom Current Sleep State (USB disconnected) LTE Cat M1 data transfer (GNSS OFF) AT+CFUN=0 @ Sleep State 0.68 - mA LTE Cat M1 DRX = 1.28 s 1.61 - mA LTE Cat NB1 DRX = 1.28 s 1.34 - mA LTE Cat M1 e-I-DRX = 81.92 s @ PTW = 20.48 s, DRX = 2.56 s 0.87 - mA LTE Cat NB1 e-I-DRX = 81.92 s @ PTW = 20.48 s, DRX = 2.56 s 1.22 - mA LTE-FDD B1 @ 21.15 dBm 184 406 mA LTE-FDD B2 @ 21.01 dBm 182 400 mA LTE-FDD B3 @ 20.
LPWA Module Series BG600L-M3 Hardware Design LTE Cat NB1 data transfer (GNSS OFF) GPRS data transfer (GNSS OFF) LTE-FDD B85 @ 21.14 dBm 185 417 mA LTE-FDD B1 @ 21.48 dBm 146 365 mA LTE-FDD B2 @ 21.5 dBm 147 379 mA LTE-FDD B3 @ 20.92 dBm 132 329 mA LTE-FDD B4 @ 20.97 dBm 133 337 mA LTE-FDD B5 @ 21.13 dBm 161 423 mA LTE-FDD B8 @ 21.35 dBm 159 408 mA LTE-FDD B12 @ 21.37 dBm 155 410 mA LTE-FDD B13 @ 21.1 dBm 164 432 mA LTE-FDD B18 @ 21.
LPWA Module Series BG600L-M3 Hardware Design EDGE data transfer (GNSS OFF) EGSM900 1UL 4DL @ 32 dBm 272 1059 mA DCS1800 4UL 1DL @ 26 dBm 402 794 mA DCS1800 3UL 2DL @ 27 dBm 321 804 mA DCS1800 2UL 3DL @ 28 dBm 253 848 mA DCS1800 1UL 4DL @ 30 dBm 182 589 mA PCS1900 4UL 1DL @ 25 dBm 414 824 mA PCS1900 3UL 2DL @ 26 dBm 331 831 mA PCS1900 2UL 3DL @ 29 dBm 271 927 mA PCS1900 1UL 4DL @ 30 dBm 193 660 mA GSM850 4UL 1DL @ 23 dBm 404 1272 mA GSM850 3UL 2DL @ 24 dBm 339 1301
LPWA Module Series BG600L-M3 Hardware Design NOTES 1. 1) The current consumption in PSM is much lower than that in power off mode, and this is because of the following two designs: More internal power supplies are powered off in PSM. Also the internal clock frequency is reduced in PSM. 2) 2. The module’s USB and UART are disconnected and GSM network does not support PSM. Table 39: GNSS Current Consumption Description Searching (AT+CFUN=0) Tracking (AT+CFUN=0) Conditions Typ.
LPWA Module Series BG600L-M3 Hardware Design NOTES 1. 2. 1) LTE-FDD B14 and B27 are supported by LTE Cat M1 only. B71 is supported by LTE Cat NB2 only. 2) LTE-FDD 5.6 RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of BG600L-M3. Table 41: BG600L-M3 Conducted RF Receiving Sensitivity (25 °C, 3.8 V) Sensitivity (dBm) Network LTE Band Primary Diversity Cat M1/3GPP Cat NB2 1)/3GPP LTE-FDD B1 -107/-102.3 -115.5/-107.5 LTE-FDD B2 -107 /-100.3 -115.5/-107.
LPWA Module Series BG600L-M3 Hardware Design LTE-FDD B28 -107 /-100.8 -115.5/-107.5 LTE-FDD B66 -108/-101.8 -116/-107.5 LTE-FDD B71 Not Supported -115/-107.5 LTE-FDD B85 -106/-99.3 -115.5/-107.5 Sensitivity (dBm) Network Band Primary Diversity GSM/3GPP GSM850/EGSM900 GSM Supported DCS1800/PCS1900 -107/-102 Not Supported -107/-102 NOTE 1) LTE Cat NB2 receiving sensitivity without repetitions. 5.
LPWA Module Series BG600L-M3 Hardware Design 6 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are ±0.05 mm unless otherwise specified. 6.1 Mechanical Dimensions 16±0.15 2.1±0.2 18.7±0.
LPWA Module Series BG600L-M3 Hardware Design 16.00±0.15 5.50 5.50 1.50 0.25 1.00 0.50 1.00 1.80 0.90 0.35 1.80 18.70±0.15 5.40 2.70 1.00 2.70 4.50 4.50 7.00 0.25 1.80 0.25 7.00 8.58 8.58 Pin 1 0.55 0.25 1.00 1.80 3.60 14x1.10 14x1.10 3.60 54x0.7 54x1.05 Figure 35: Module Bottom Dimensions (Bottom View) NOTE The package warpage level of the module conforms to JEITA ED-7306 standard.
LPWA Module Series BG600L-M3 Hardware Design 6.2 Recommended Footprint 16.00±0.15 5.50 1.00 5.50 0.50 1.50 0.25 1.00 7.00 7.00 1.80 4.50 2.70 1.80 5.40 0.90 0.35 2.70 1.00 4.50 0.25 8.58 1.80 8.58 Pin 1 0.25 0.55 1.00 1.80 3.60 54x0.7 54x1.05 0.25 3.60 14x1.10 14x1.10 Figure 36: Recommended Footprint (Top View) NOTES 1. 2. For easy maintenance of the module, please keep about 3 mm between the module and other components on the motherboard. All reserved pins must be kept open.
LPWA Module Series BG600L-M3 Hardware Design 6.3 Top and Bottom Views Figure 37: Top View of the Module Figure 38: Bottom View of the Module NOTE These are renderings of BG600L-M3 module. For authentic appearance, please refer to the module received from Quectel.
LPWA Module Series BG600L-M3 Hardware Design 7 Storage, Manufacturing and Packaging 7.1 Storage BG600L-M3 is provided with vacuum-sealed packaging. MSL of the module is rated as 3. The storage requirements are shown below. 1. Recommended Storage Condition: The temperature should be 23 ±5 °C and the relative humidity should be 35%–60%. 2. The storage life (in vacuum-sealed packaging) is 12 months in Recommended Storage Condition. 3.
LPWA Module Series BG600L-M3 Hardware Design NOTE Please take the module out of the packaging and put it on high-temperature resistant fixtures before the baking. If shorter baking time is desired, please refer to IPC/JEDEC J-STD-033 for baking procedure. 7.2 Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB.
LPWA Module Series BG600L-M3 Hardware Design Table 43: Recommended Thermal Profile Parameters Factor Recommendation Soak Zone Max slope 1–3 °C/s Soak time (between A and B: 150°C and 200°C) 70–120 s Reflow Zone Max slope 2–3 °C/s Reflow time (D: over 220°C) 45–70 s Max temperature 238–246 °C Cooling down slope -1 to -4 °C/s Reflow Cycle Max reflow cycle 1 7.3 Packaging BG600L-M3 is packaged in a vacuum-sealed bag which is ESD protected.
LPWA Module Series BG600L-M3 Hardware Design Figure 40: Tape Dimensions Figure 41: Reel Dimensions BG600L-M3_Hardware_Design 79 / 83
LPWA Module Series BG600L-M3 Hardware Design Table 44: Module Packaging Specifications MOQ for MP Minimum Package: 250 Minimum Package x 4 = 1000 250 Size: 370 mm × 350 mm × 56 mm N.W: TBD G.W: TBD Size: 380 mm × 250 mm × 365 mm N.W: TBD G.
LPWA Module Series BG600L-M3 Hardware Design 8 Appendix A References Table 45: Related Documents SN Document Name Remark [1] Quectel_UMTS<E_EVB_User_Guide UMTS<E EVB User Guide [2] Quectel_BG95&BG77&BG600L&BC69_Series_AT_ Commands_Manual AT Commands Manual of BG95 series, BG77, BG600L-M3 and BC69 modules [3] Quectel_ BG95&BG77&BG600L&BC69_Series_ GNSS_Application_Note GNSS Application Note of BG95 series, BG77, BG600L-M3 and BC69 modules [4] Quectel_RF_Layout_Application_Note RF Layout
LPWA Module Series BG600L-M3 Hardware Design ESD Electrostatic Discharge FDD Frequency Division Duplex FR Full Rate GMSK Gaussian Minimum Shift Keying GSM Global System for Mobile Communications HSS Home Subscriber Server I/O Input/Output Inorm Normal Current LED Light Emitting Diode LNA Low Noise Amplifier LTE Long Term Evolution MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Proto
LPWA Module Series BG600L-M3 Hardware Design TX Transmitting Direction UL Uplink UE User Equipment URC Unsolicited Result Code (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin
LPWA Module Series BG600L-M3 Hardware Design 9 Appendix B GPRS Coding Schemes Table 47: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
LPWA Module Series BG600L-M3 Hardware Design 10 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
LPWA Module Series BG600L-M3 Hardware Design 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 BG600L-M3_Hardware_Design 86 / 83
LPWA Module Series BG600L-M3 Hardware Design 11 Appendix D EDGE Modulation and Coding Schemes Table 49: EDGE Modulation and Coding Schemes Coding Schemes Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1 GMSK / 9.05 kbps 18.1 kbps 36.2 kbps CS-2 GMSK / 13.4 kbps 26.8 kbps 53.6 kbps CS-3 GMSK / 15.6 kbps 31.2 kbps 62.4 kbps CS-4 GMSK / 21.4 kbps 42.8 kbps 85.6 kbps MCS-1 GMSK C 8.80 kbps 17.60 kbps 35.20 kbps MCS-2 GMSK B 11.2 kbps 22.4 kbps 44.
