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Smart LTE Module Series
SC20 Hardware Design
SC20_Hardware_Design 51 / 130
3.13. GPIO Interfaces
SC20 has abundant GPIO interfaces with logic level of 1.8V. The pin definition is listed below.
Table 16: Pin Definition of GPIO Interfaces
43
SD_DATA2
14.53
44
SD_DATA3
14.57
PIN
Pin Name
GPIO
Default state
Comment
30
TP_INT
GPIO_13
B-PD: nppukp
1)
Wakeup
2)
31
TP_RST
GPIO_12
B-PD: nppukp
Wakeup
33
GPIO_23
GPIO_23
B-PD: nppukp
34
UART1_TX
GPIO_20
B-PD: nppukp
Wakeup
35
UART1_RX
GPIO_21
B-PD: nppukp
UART1_RX Wakeup
36
UART1_CTS
GPIO_111
B-PD: nppukp
Wakeup
37
UART1_RTS
GPIO_112
B-PD: nppukp
Wakeup
45
SD_DET
GPIO_38
B-PD: nppukp
Wakeup
47
TP_I2C_SCL
GPIO_19
B-PD: nppukp
48
TP_I2C_SDA
GPIO_18
B-PD: nppukp
49
LCD_RST
GPIO_25
B-PD: nppukp
Wakeup
50
LCD_TE
GPIO_24
B-PD: nppukp
74
CAM0_CLK
GPIO_26
B-PD: nppukp
75
CAM1_CLK
GPIO_27
B-PD: nppukp
79
CAM0_RST
GPIO_35
B-PD: nppukp
Wakeup
80
CAM0_PWD
GPIO_34
B-PD: nppukp
Wakeup
81
CAM1_RST
GPIO_28
B-PD: nppukp
Wakeup