Product Info

LTE Module Series
EC25 Hardware Design
EC25_Hardware_Design 68 / 112
4. “*” means under development.
5.
1)
Pads 24~27 are multiplexing pins used for audio design on EC25 module and BT function on BT
module.
3.19.1. WLAN Interface
EC25 provides a low power SDIO 3.0 interface and control interface for WLAN design.
SDIO interface supports the SDR mode (up to 50MHz).
As SDIO signals are very high-speed, in order to ensure the SDIO interface design corresponds with the
SDIO 3.0 specification, please comply with the following principles:
 It is important to route the SDIO signal traces with total grounding. The impedance of SDIO signal
trace is 50Ω±10%.
 Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
 etc., as well as noisy signals such as clock signals, DCDC signals, etc.
 It is recommended to keep matching length between CLK andDATA/CMD less than 1mm and total
routing length less than 50mm.
 Keep termination resistors within 15Ω~24Ω on clock lines near the module and keep the route
distance from the module clock pins to termination resistors less than 5mm.
 Make sure the adjacent trace spacing is 2 times of the trace width and bus capacitance is less than
15pF.

WLAN is an optional function for EC25-AF which not included in current product.
3.19.2. BT Interface*
EC25 supports a dedicated UART interface and a PCM interface for BT application.
Further information about BT interface will be added in future version of this document.
“*” means under development.
BT is an optional function for EC25-AF which not included in current product.
NOTE
NOTE