Product Info

LTE Module Series
EC25 Hardware Design
EC25_Hardware_Design 57 / 112
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048KHz PCM_CLK and 8KHz PCM_SYNC. Please refer to
document [2] for more details about AT+QDAI command.
The following figure shows a reference design of PCM interface with external codec IC.
Figure 24: Reference Circuit of PCM Application with Audio Codec
1. It is recommended to reserve an RC (R=22Ω, C=22pF) circuits on the PCM lines, especially for
PCM_CLK.
2. EC25 works as a master device pertaining to I2C interface.
PCM_OUT 25 DO PCM data output 1.8V power domain
PCM_SYNC 26 IO
PCM data frame
synchronization signal
1.8V power domain
PCM_CLK 27 IO PCM data bit clock 1.8V power domain
I2C_SCL 41 OD I2C serial clock Require external pull-up to 1.8V
I2C_SDA 42 OD I2C serial data Require external pull-up to 1.8V
NOTES