Product Info

LTE Module Series
EC25 Mini PCIe Hardware Design
EC25_Mini_PCIe_Hardware_Design Confidential / Released 28 / 46
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. In addition, EC25
Mini PCIe’s firmware has integrated the configuration on some PCM codec’s application with I2C interface.
Please refer to document [2] for details about AT+QDAI command.
The following figure shows a reference design of PCM interface with an external codec IC.
Figure 8: Reference Circuit of PCM Application with Audio Codec
3.8. Control Signals
The following table shows the pin definition of control signals.
Table 10: Pin Definition of Control Signals
Pin No. Pin Name I/O Power Domain Description
17 RI DO 3.3V
Output signal can be used to wake up
the host.
31 DTR DI 3.3V Sleep mode control
20 W_DISABLE# DI 3.3V
Disable wireless communications;
pull-up by default, active low.
22 PERST# DI 3.3V Functional reset to the card; active low.
42 LED_WWAN# OC
Active-low. LED signal for indicating the
state of the module.
1 WAKE# OC
Output signal can be used to wake up
the host.