Product Info

LTE Standard Module Series
EC21 Mini PCIe Hardware Design
EC21_Mini_PCIe_Hardware_Design 31 / 64
Figure 7: Timing in Primary Mode
In auxiliary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising
edge. The PCM_SYNC rising edge represents the MSB. In this mode, the PCM interface operates with a
256KHz, 512KHz, 1024KHz or 2048KHz PCM_CLK and an 8KHz, 50% duty cycle PCM_SYNC. The
following figure shows the timing relationship in auxiliary mode with 8KHz PCM_SYNC and 256KHz
PCM_CLK.
Figure 8: Timing in Auxiliary Mode
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048KHz PCM_CLK and 8KHz PCM_SYNC. In addition, EC21
Mini PCIe’s firmware has integrated the configuration on some PCM codec’s application with I2C interface.
Please refer to document [2] for details about AT+QDAI command.