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LTE Standard Module Series
EC21 Hardware Design
EC21_Hardware_Design 11 / 120
Figure Index
FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 23
FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 25
FIGURE 3: SLEEP MODE APPLICATION VIA UART ....................................................................................... 39
FIGURE 4: SLEEP MODE APPLICATION WITH USB REMOTE WAKEUP .................................................... 40
FIGURE 5: SLEEP MODE APPLICATION WITH RI ......................................................................................... 40
FIGURE 6: SLEEP MODE APPLICATION WITHOUT SUSPEND FUNCTION ................................................ 41
FIGURE 7: POWER SUPPLY LIMITS DURING BURST TRANSMISSION ...................................................... 43
FIGURE 8: STAR STRUCTURE OF THE POWER SUPPLY ............................................................................ 43
FIGURE 9: REFERENCE CIRCUIT OF POWER SUPPLY .............................................................................. 44
FIGURE 10: TURN ON THE MODULE BY USING DRIVING CIRCUIT ........................................................... 45
FIGURE 11: TURN ON THE MODULE BY USING KEYSTROKE .................................................................... 46
FIGURE 12: TIMING OF TURNING ON MODULE ........................................................................................... 46
FIGURE 13: TIMING OF TURNING OFF MODULE ......................................................................................... 47
FIGURE 14: REFERENCE CIRCUIT OF RESET_N BY USING DRIVING CIRCUIT ...................................... 48
FIGURE 15: REFERENCE CIRCUIT OF RESET_N BY USING BUTTON ...................................................... 49
FIGURE 16: TIMING OF RESETTING MODULE ............................................................................................. 49
FIGURE 17: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH AN 8-PIN (U)SIM CARD CONNECTOR
................................................................................................................................................................... 50
FIGURE 18: REFERENCE CIRCUIT OF (U)SIM INTERFACE WITH A 6-PIN (U)SIM CARD CONNECTOR . 51
FIGURE 19: REFERENCE CIRCUIT OF USB APPLICATION ......................................................................... 52
FIGURE 20: REFERENCE CIRCUIT WITH TRANSLATOR CHIP ................................................................... 54
FIGURE 21: REFERENCE CIRCUIT WITH TRANSISTOR CIRCUIT .............................................................. 55
FIGURE 22: PRIMARY MODE TIMING ............................................................................................................ 56
FIGURE 23: AUXILIARY MODE TIMING .......................................................................................................... 56
FIGURE 24: REFERENCE CIRCUIT OF PCM APPLICATION WITH AUDIO CODEC .................................... 57
FIGURE 25: REFERENCE CIRCUIT OF SD CARD INTERFACE .................................................................... 58
FIGURE 26: REFERENCE CIRCUIT OF WIRELESS CONNECTIVITY INTERFACES WITH FC20 MODULE
................................................................................................................................................................... 61
FIGURE 27: SIMPLIFIED BLOCK DIAGRAM FOR ETHERNET APPLICATION ............................................. 64
FIGURE 28: REFERENCE CIRCUIT OF SGMII INTERFACE WITH PHY AR8033 APPLICATION ................. 65
FIGURE 29: REFERENCE CIRCUIT OF THE NETWORK INDICATOR .......................................................... 67
FIGURE 30: REFERENCE CIRCUITS OF STATUS ......................................................................................... 68
FIGURE 31: REFERENCE CIRCUIT OF USB_BOOT INTERFACE ................................................................ 69
FIGURE 32: TIMING SEQUENCE FOR ENTERING EMERGENCY DOWNLOAD MODE ............................. 70
FIGURE 33: REFERENCE CIRCUIT OF RF ANTENNA INTERFACE ............................................................. 75
FIGURE 34: MICROSTRIP DESIGN ON A 2-LAYER PCB ............................................................................... 76
FIGURE 35: COPLANAR WAVEGUIDE DESIGN ON A 2-LAYER PCB ........................................................... 76
FIGURE 36: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 3 AS REFERENCE GROUND)
................................................................................................................................................................... 76
FIGURE 37: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND)
................................................................................................................................................................... 77