Product Info
Table Of Contents
- About the Document
- Contents
- Table Index
- Figure Index
- 1 Introduction
- 2 Product Concept
- 3 Application Interfaces
- 3.1. General Description
- 3.2. Pin Assignment
- 3.3. Pin Description
- 3.4. Power Supply
- 3.5. Turn on and off Scenarios
- 3.6. VRTC Interface
- 3.7. Power Output
- 3.8. Battery Charge and Management
- 3.9. USB Interfaces
- 3.10. UART Interfaces
- 3.11. (U)SIM Interfaces
- 3.12. SD Card Interface
- 3.13. GPIO Interfaces
- 3.14. I2C Interfaces
- 3.15. I2S Interfaces
- 3.16. SPI Interface
- 3.17. ADC Interfaces
- 3.18. LCM Interfaces
- 3.19. Touch Panel Interfaces
- 3.20. Camera Interfaces
- 3.21. Sensor Interfaces
- 3.22. Audio Interfaces
- 3.23. Emergency Download Interface
- 4 Wi-Fi and BT
- 5 GNSS
- 6 Antenna Interfaces
- 7 Electrical, Reliability and Radio Characteristics
- 8 Mechanical Dimensions
- 9 Storage, Manufacturing and Packaging
- 10 Appendix A References
- 11 Appendix B GPRS Coding Schemes
- 12 Appendix C GPRS Multi-slot Classes
- 13 Appendix D EDGE Modulation and Coding Schemes
- IC & FCC Requirement
Smart LTE Module Series
SC66 Hardware Design
SC66_Hardware_Design 69 / 139
3.18. LCM Interfaces
SC66 video output interface (LCM interface) is based on MIPI_DSI standard and supports 8 groups of
high-speed differential data transmission and WQXGA display (resolution: 2560 × 1600), Support dual
display, default DSI+DP (Type-C), optional DSI0+DSI1. Note that DSI1 does not support screens with
command mode.
Table 25: Pin Definition of LCM Interfaces
Pin Name Pin No. I/O Description Comment
LDO11A_1P8 10 PO
1.8V output power supply
for LCM logic circuit and
DSI
LDO3B_2P8 12 PO
2.8V output power supply
for LCM analog circuits
PWM 152 DO PWM signal output
Cannot be multiplexed into
a general-purpose GPIO.
LCD0_RST 127 DO LCD0 reset signal It should not be pulled up.
LCD0_TE 126 DI LCD0 tearing effect signal
DSI0_CLK_N 116 AO
LCD0 MIPI clock signal (-)
DSI0_CLK_P 115 AO
LCD0 MIPI clock signal
(+)
DSI0_LN0_N 118 AO
LCD0 MIPI lane 0 data
signal (-)
DSI0_LN0_P 117 AO
LCD0 MIPI lane 0 data
signal (+)
DSI0_LN1_N 120 AO
LCD0 MIPI lane 1 data
signal (-)
DSI0_LN1_P 119 AO
LCD0 MIPI lane 1 data
signal (+)
DSI0_LN2_N 122 AO LCD0 MIPI lane 2 data