Product Info

Smart LTE Module Series
SC66 Hardware Design
SC66_Hardware_Design 37 / 139
of front camera (-)
impedance.
CSI0_LN0_P 79 AI
MIPI lane 0 data signal
of front camera (+)
CSI0_LN1_N 82 AI
MIPI lane 1 data signal
of front camera (-)
85Ω differential
impedance.
CSI0_LN1_P 81 AI
MIPI lane 1 data signal
of front camera (+)
CSI0_LN2_N 84 AI
MIPI lane 2 data signal
of front camera (-)
85Ω differential
impedance.
CSI0_LN2_P 83 AI
MIPI lane 2 data signal
of front camera (+)
CSI0_LN3_N 86 AI
MIPI lane 3 data signal
of front camera (-)
85Ω differential
impedance.
CSI0_LN3_P 85 AI
MIPI lane 3 data signal
of front camera (+)
MCAM_MCLK 99 DO
Master clock signal of
rear camera
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
SCAM_MCLK 100 DO
Master clock signal of
front camera
1.8V power domain.
MCAM_RST 74 DO
Reset signal of rear
camera
1.8V power domain.
MCAM_PWDN 73 DO
Power down signal of
rear camera
1.8V power domain.
SCAM_RST 72 DO
Reset signal of front
camera
1.8V power domain.
SCAM_PWDN 71 DO
Power down signal of
front camera
1.8V power domain.
CAM_I2C_SCL
0
75 OD
I2C clock signal of
camera
1.8V power domain.
CAM_I2C_SDA
0
76 OD
I2C data signal of
camera
1.8V power domain.
DCAM_MCLK 194 DO
Master clock signal of
depth camera
V
OL
max=0.45V
V
OH
min=1.35V
1.8V power domain.
DCAM_RST 180 DO Reset signal of depth 1.8V power domain.