Product Info
Table Of Contents
- About the Document
- Contents
- Table Index
- Figure Index
- 1 Introduction
- 2 Product Concept
- 3 Application Interfaces
- 3.1. General Description
- 3.2. Pin Assignment
- 3.3. Pin Description
- 3.4. Operating Modes
- 3.5. Power Saving
- 3.6. Power Supply
- 3.7. Power-on/off Scenarios
- 3.8. Reset the Module
- 3.9. (U)SIM Interfaces
- 3.10. USB Interface
- 3.11. UART Interfaces
- 3.12. PCM and I2C Interfaces
- 3.13. SPI Interface
- 3.14. Network Status Indication
- 3.15. STATUS
- 3.16. ADC Interface
- 3.17. Behaviors of RI
- 3.18. USB_BOOT Interface
- 4 GNSS Receiver
- 5 Antenna Interfaces
- 6 Electrical, Reliability and Radio Characteristics
- 7 Mechanical Dimensions
- 8 Storage, Manufacturing and Packaging
- 9 Appendix A References
- 10 Appendix B GPRS Coding Schemes
- 11 Appendix C GPRS Multi-slot Classes
- 12 Appendix D EDGE Modulation and Coding Schemes
LTE Standard Module Series
EG91 Hardware Design
EG91_Hardware_Design 42 / 93
3.11. UART Interfaces
The module provides two UART interfaces: the main UART interface and the debug UART interface. The
following shows their features.
The main UART interface supports 9600bps, 19200bps, 38400bps, 57600bps, 115200bps,
230400bps, 460800bps, 921600bps and 3000000bps baud rates, and the default is 115200bps. It
supports RTS and CTS hardware flow control, and is used for AT command communication only.
The debug UART interface supports 115200bps baud rate. It is used for Linux console and log output.
The following tables show the pin definition of the two UART interfaces.
Table 11: Pin Definition of Main UART Interfaces
Pin Name
Pin No. I/O Description Comment
RI 39 DO Ring indicator
1.8V power domain
DCD 38 DO Data carrier detection
CTS 36 DO Clear to send
RTS 37 DI Request to send
DTR 30 DI Sleep mode control
TXD 35 DO Transmit data
RXD 34 DI Receive data
Table 12: Pin Definition of Debug UART Interface
Pin Name Pin No. I/O Description Comment
DBG_TXD 23 DO Transmit data 1.8V power domain
DBG_RXD 22 DI Receive data 1.8V power domain
The logic levels are described in the following table.