Product Info

Automotive Module Series
AG35 Hardware Design
AG35_Hardware_Design 67 / 129
trace is 50Ω (±10%).
 Keep SDIO signals far away from other sensitive circuits/signals such as RF circuits, analog signals,
etc., as well as noisy signals such as clock signals, DCDC signals, etc.
 It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm
and the total routing length less than 50mm. The total length of SDIO signal traces inside AG35
module is 12mm and that inside AF20 is 10mm, so the exterior total trace length should be less than
28mm.
 Keep termination resistors within 15~24Ω on clock lines near the module and keep the route distance
from the module clock pins to termination resistors less than 5mm.
 Make sure the adjacent trace spacing is two times of the trace width and the bus capacitance is less
than 40pF.
3.16.2. BT Interface*
More information about BT interface will be added in the future version of this document.
“*” means under development.
3.17. ADC Interfaces
The module provides three analog-to-digital converter (ADC) interfaces. The voltage value on ADC pins
can be read via AT+QADC=<port> command, through setting <port> into 0, 1 or 2. For more details
about the AT command, please refer to document [2].
 AT+QADC=0: read the voltage value on ADC0
 AT+QADC=1: read the voltage value on ADC1
 AT+QADC=2: read the voltage value on ADC2
In order to improve the accuracy of ADC, the trace of ADC interfaces should be surrounded by ground.
Table 23: Pin Definition of ADC Interfaces
Pin Name
Pin No.
Description
ADC2
172
General purpose analog to digital converter interface
ADC0
173
General purpose analog to digital converter interface
NOTE