Product Info

Automotive Module Series
AG35 Hardware Design
AG35_Hardware_Design 63 / 129
Module
AR8033
Ethernet
Transformer
RJ45
SGMII
Control
MDI
Figure 25: Simplified Block Diagram for Ethernet Application
The following figure shows a reference design of SGMII interface with PHY AR8033 application.
MDIO_DATA
EPHY_INT_N
MDIO
RSTN
MDC
R1
R2
10K
VDD_EXT
Module
AR8033
1.5K
VDD_MDIO
EPHY_RST_N
INT
MDIO_CLK
C3
C4
SGMII_TX_M
SGMII_TX_P
SGMII_RX_P
SGMII_RX_M
SIP
SIN
SOP
SON
Close to AR8033
Control
SGMII Data
Figure 26: Reference Circuit of SGMII Interface with PHY AR8033 Application
In order to enhance the reliability and availability of customers’ application, please follow the criteria below
in the Ethernet PHY circuit design:
 Keep SGMII data and control signals away from RF and VBAT traces.
 Keep the maximum trace length less than 10 inches and keep skew on the differential pairs less than
20 mils.
 The differential impedance of SGMII data trace is 100Ω±10%.
 To minimize crosstalk, the distance between separate adjacent pairs that are on the same layer must
be equal to or larger than 40 mils.