Product Info

Automotive Module Series
AG35 Hardware Design
AG35_Hardware_Design 62 / 129
3.15. SGMII Interface (Optional)
AG35 includes an integrated Ethernet MAC with an SGMII interface and two management interfaces. Key
features of the SGMII interface are shown below:
 IEEE802.3 compliance
 Half/full duplex for 10/100/1000Mbps
 Support VLAN tagging
 Support IEEE1588 and Precision Time Protocol (PTP)
 Can be connected to an external Ethernet PHY like AR8033, or an external switch
 Management interfaces support dual power domains: 1.8V and 2.85V.
The following table shows the pin definition of SGMII interface.
Table 21: Pin Definition of SGMII Interface
The following figure shows the simplified block diagram for Ethernet application.
Pin Name
Pin No.
I/O
Description
Comment
MDIO Interface
EPHY_RST_N
6
DO
Ethernet PHY reset
1.8V/2.85V power domain
EPHY_INT_N
9
DI
Ethernet PHY interrupt
1.8V power domain
SGMII_
MDATA
8
IO
SGMII MDIO (Management
Data Input/Output) data
1.8V/2.85V power domain
SGMII_MCLK
7
DO
SGMII MDIO (Management
Data Input/Output) clock
1.8V/2.85V power domain
VDD_MDIO
4
PO
SGMII MDIO pull-up power
source
1.8V/2.85V power domain.
External pull-up power source
for SGMII MDIO pins.
SGMII Signal Part
SGMII_TX_M
15
AO
SGMII transmission (-)
Connect with a 0.1uF capacitor,
close to the PHY side.
SGMII_TX_P
14
AO
SGMII transmission (+)
Connect with a 0.1uF capacitor,
close to the PHY side.
SGMII_RX_P
12
AI
SGMII receiving (+)
SGMII_RX_M
11
AI
SGMII receiving (-)