Product Info

LTE-A Module Series
EM06 Hardware Design
EM06_Hardware_Design 33 / 63
PCM_CLK
PCM_SYNC
PCM_OUT
MSB
LSB
PCM_IN
125us
MSB
1 2 3231
LSB
Figure 18: Auxiliary Mode Timing
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Table 10: Pin Definition of PCM and I2C Interfaces
Pin Name
Pin No.
I/O
Description
Comment
PCM_IN
22
DI
PCM data input
1.8V power domain.
PCM_OUT
24
DO
PCM data output
1.8V power domain.
PCM_SYNC
28
IO
PCM data frame
synchronization signal
1.8V power domain.
PCM_CLK
20
IO
PCM data bit clock
1.8V power domain.
In master mode, it is an output
signal. In slave mode, it is an
input signal.
If unused, keep it open.
I2C_SCL
58
DO
I2C serial clock
Used for external codec.
Require an external pull-up to
1.8V.
I2C_SDA
56
IO
I2C serial data
The clock and mode can be configured by AT command, and the default configuration is master mode
using short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to
document [2] for details about AT+QDAI command.
The following figure shows a reference design of PCM interface with an external codec IC.