Product Info

LTE Module Series
BG96 Hardware Design
BG96_Hardware_Design 48 / 81
Table 14:Logic Levels of Digital I/O
The module provides 1.8V UART interface. A level translator should be used if
customers’application is equipped with a 3.3V UART interface. A level
translator TXS0108EPWR provided by Texas Instrumentsis recommended.
The following figure shows a reference design.
Figure 16: Reference Circuit with Translator Chip
Please visit http://www.ti.com
formore information.
Another example with transistor translation circuit is shown as below.
Thecircuitdesign of dotted line section can refer to thatof solid line section, in
Parameter Min. Max. Unit
V
IL
-0.3 0.6 V
V
IH
1.2 2.0 V
V
OL
0 0.45 V
V
OH
1.35 1.8 V