Product Info

LPWA Module Series
BG95 Series Hardware Design
BG95_Series_Hardware_Design 55 / 106
Table 20: Pin Definition of STATUS
The following figure shows a reference circuit of STATUS.
4.7K
47K
VBAT
2.2K
Module
STATUS
Figure 22: Reference Design of STATUS
3.15. Behaviors of MAIN_RI
AT+QCFG="risignaltype","physical" command can be used to configure MAIN_RI pin behavior.
No matter on which port the URC is presented, the URC will trigger the behavior of MAIN_RI pin. The
default behaviors of MAIN_RI pin are shown as below.
Table 21: Default Behaviors of MAIN_RI Pin
The default MAIN_RI pin behaviors can be configured flexibly by AT+QCFG="urc/ri/ring" command. For
more details about AT+QCFG*, see document [2].
1. URC can be outputted from UART port, USB AT port and USB modem port, through configuration via
AT+QURCCFG command. The default port is USB AT port.
Pin Name
Pin No.
I/O
Description
Comment
STATUS
20
DO
Module operation status indication
1.8 V power domain
State
Response
Idle
MAIN_RI keeps in high level.
URC
MAIN_RI outputs 120 ms low pulse when a new URC returns.
NOTES