Product Info

LPWA Module Series
BG95 Series Hardware Design
BG95_Series_Hardware_Design 37 / 106
MAIN_RXD
MAIN_TXD
MAIN_RI
MAIN_DTR
AP_READY
TXD
RXD
EINT
GPIO
GPIO
Module
Host
GND
GND
Figure 3: Sleep Mode Application via UART
⚫ When the module has URC to report, MAIN_RI signal wakes up the host. See Chapter 3.15 for
details about MAIN_RI behavior.
⚫ Driving MAIN_DTR low wakes up the module.
⚫ AP_READY* detects the sleep state of the host (can be configured to high level or low level
detection). See AT+QCFG="apready" command in document [2] for details.
“*” means under development.
3.5. Power Supply
3.5.1. Power Supply Pins
BG95 provides the following four VBAT pins for connection with an external power supply. There are two
separate voltage domains for VBAT.
⚫ Two VBAT_RF pins for module’s RF part.
⚫ Two VBAT_BB pins for module’s baseband part.
The following table shows the details of VBAT pins and ground pins.
NOTE