Product Info

1
.
2
.
EG95_Seri
e
.
Please
m
the time
.
When u
s
above ti
m
VBAT.
C
downloa
d
NOTES
e
s_Hardw
a
VBAT
PWR
K
RESE
T
VDD_
E
USB_
B
Figure
2
m
ake sure t
h
between p
o
s
ing MCU t
o
m
ing seque
n
C
onnect the
d
mode.
a
re_Design
Mo
d
US
B
Figure 28
:
K
EY
T
_N
E
XT
B
OOT
NOT
E
2
9: Timing
h
at VBAT i
s
o
wering up
V
o
control m
n
ce. It is no
t
test points
d
ule
B
_BOOT
T
V
:
Referenc
e
USB
_
VDD
_
ente
r
pow
e
E
1
≥ 500
m
V
IL
≤ 0.
5
About 1
0
Sequence
f
s
stable bef
o
V
BAT and p
u
odule to e
n
t
recommen
as shown
5
Test points
V
S
Close to tes
t
e
Circuit of
_
BOOT can
b
_
EXT Is pow
e
r
emergency
e
red on.
m
s
5
V
V
H
=
0
0 ms
f
or Enterin
g
o
re pulling
d
u
lling down
n
ter the em
e
ded to pull
u
in Figure
2
5
9 / 103
4.7K
t
points
USB_BOO
T
b
e pulled up t
o
e
red up, and t
h
download m
o
=
0.8 V
g
Emergen
c
d
own PWR
K
PWRKEY p
e
rgency do
w
u
p USB_B
O
28
can man
LTE St
a
EG95 Se
r
VDD_EXT
T
Interface
o
1.8 V befor
e
h
e module wil
l
o
de when it i
s
c
y Downlo
a
K
EY pin. It i
s
in is no les
s
w
nload mo
d
O
OT to 1.8
V
ually force
a
ndard Mo
d
r
ies Hard
w
e
l
s
a
d Mode
s
recomme
n
s
than 30ms
.
d
e, please
f
V
before po
w
the modul
e
d
ule Serie
s
w
are Desig
n
n
ded that
.
f
ollow the
w
ering up
e
to enter
s
n