Product Info

EG95_Seri
e
The followi
n
codec desi
g
Table 14:
P
Pin Name
PCM_DIN
PCM_DO
U
PCM_SY
N
PCM_CL
K
I2C_SCL
I2C_SDA
Clock and
m
short fram
e
document
[
The followi
n
e
s_Hardw
a
PCM
_
PCM
_
PCM
_
PCM
_
n
g table sh
o
g
n.
P
in Definiti
o
Pin
N
6
U
T 7
N
C 5
K
4
40
41
m
ode can b
e
e
synchroni
[
2] aboutA
T
n
g figure sh
o
a
re_Design
_
CLK
_
SYNC
_
DOUT
_
DIN
o
ws the pin
o
n of PCM
a
N
o. I/O
DI
DO
IO
IO
OD
OD
e
configure
d
zationform
a
T
+QDAIcom
o
ws arefere
n
MS B
MS B
12
Figure 23:
A
definition
o
a
nd I2C Int
e
Descri
PCM d
PCM d
PCM d
synchr
o
PCM d
I2C se
r
I2C se
r
d
by AT co
m
a
t with 204
8
mand for d
e
n
ce design
o
5
125 μs
A
uxiliary
M
o
f PCM and
e
rfaces
ption
ata input
ata output
ata frame
o
nization si
g
ata bit cloc
k
r
ial clock
r
ial data
m
mand, and
8
kHzPCM
_
e
tails.
o
f PCM and
5
3 / 103
L
3
31
L
M
ode Timin
g
I2C interfa
c
C
1
1
g
nal
1
k
1
A
r
e
A
r
e
the default
_
CLK and
I2C interfa
c
LTE St
a
EG95 Se
r
L
SB
32
L
SB
g
c
es which
c
C
omment
.8 V power
.8 V power
.8 V power
.8 V power
A
n external
p
e
quired.
A
n external
p
e
quired.
configurati
o
8 kHzPCM
_
c
es with ext
e
a
ndard Mo
d
r
ies Hard
w
c
an be appli
domain
domain
domain
domain
p
ull-up to 1.
8
p
ull-up to 1.
8
o
n is master
_
SYNC.Ple
a
e
rnal codec
d
ule Serie
s
w
are Desig
n
ed on audi
o
8
V is
8
V is
mode usin
g
a
se
r
efer t
o
IC.
s
n
o
g
o