User's Manual

LTE Module Series
EC25Hardware Design
EC25_Hardware_DesignConfidential / Released 56 / 90
As SDIO signals are very high-speed, in order to ensure the SDIO interface design corresponds with the
SDIO 3.0 specification, please comply with the following principles:
 It is important to route the SDIO signal traces with total grounding. The impedance of SDIOsignal
trace is 50ohm(±10%).
 Protect other sensitive signals/circuits(RF, analog signals, etc.) from SDIO corruption and protect
SDIO signals from noisy signals (clocks, DCDCs, etc.).
 It is recommended to keep matching lengthbetween CLK andDATA/CMD less than 1mm and total
routing length less than 50mm.
 Keep termination resistorswithin 15~24ohm on clock lines near the module and keep the route
distance from the module clock pins to termination resistorsless than 5mm.
 Make sure the adjacent trace spacing is 2x line width and bus capacitance is less than 15pF.
3.18.2. BT Interface*
EC25 supportsa dedicated UART interface and a PCM interface for BT application.
Further information about BT interface will be added in future version of this document.
“*” means under development.
3.19. USB_BOOT Interface
EC25 provides a USB_BOOT pin. During development or factory production, USB_BOOT pin can force
the module to boot from USB port for firmware upgrade.
Table 23: Pin Definition of USB_BOOT Interface
Pin Name Pin No. I/O Description Comment
USB_BOOT 115 DI
Force the module to boot from USB
port
1.8V power domain.
Active high.
If unused, keep it open.
NOTE