User's Manual

LTE Module Series
EC25Hardware Design
EC25_Hardware_DesignConfidential / Released 52 / 90
SGMII_RX_P 125 AI SGMII receiving-plus
Connect with a 0.1uF capacitor,
close to EC25 module.
SGMII_RX_M 126 AI SGMII receiving-minus
Connect with a 0.1uF capacitor,
close to EC25 module.
The following figure shows the simplified block diagram for Ethernet application.
Figure 27: Simplified Block Diagram for Ethernet Application
The following figure shows a reference design ofSGMII interface with PHY AR8033 application.
SGMII_MDATA
EPHY_INT_N
MDIO
RSTN
MDC
R1
R2
10K
VDD_EXT
Module
AR8033
1.5K
USIM2_VDD
EPHY_RST_N
INT
SGMII_MCLK
C1
C2
C3
C4
SGMII_TX_M
SGMII_TX_P
SGMII_RX_P
SGMII_RX_M
SIP
SIN
SOP
SON
Close to Module
Close to AR8033
Control
SGMII Data
0.1uF
0.1uF
0.1uF
0.1uF
USIM2_VDD
USIM2_VDD
Figure 28: Reference Circuit of SGMII Interface with PHY AR8033 Application
In order to enhance the reliability and availability in your application, please follow the criteria below in the
Ethernet PHY circuit design:
 Keep SGMII data and control signals away from RF and VBAT trace.
 Keep the maximum trace length less than 10inch and keep skew on the differential pairs less than