User's Manual

LTE Module Series
EC25Hardware Design
EC25_Hardware_DesignConfidential / Released 47 / 90
PCM_CLK 27 IO PCM data bit clock 1.8V power domain
I2C_SCL 41 OD I2C serial clock Require external pull-up to 1.8V
I2C_SDA 42 OD I2C serial data Require external pull-up to 1.8V
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHzPCM_CLK and 8kHz PCM_SYNC.Please refer to
document [2] about AT+QDAIcommand for details.
The following figure shows areference design of PCM interface with external codec IC.
Figure 24: Reference Circuit of PCM Application with Audio Codec
1. “*” means under development.
2. It is recommended to reserve RC (R=22ohm, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
3. EC25 works as a master device pertaining to I2C interface.
3.13. ADC Function
The module provides two analog-to-digital converters (ADC).AT+QADC=0command can be used toread
the voltage value on ADC0 pin. AT+QADC=1command can be used to read the voltage value on ADC1
pin. For more details about these AT commands, please refer todocument [2].
In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground.
NOTES