User's Manual

LTE Module Series
EC21 Hardware Design
EC21_Hardware_Design Confidential / Released 53 / 94
Figure 28: Reference Circuit of SGMII Interface with PHY AR8033 Application
In order to enhance the reliability and availability in your application, please follow the criteria below in the
Ethernet PHY circuit design:
 Keep SGMII data and control signals away from RF and VBAT trace.
 Keep the maximum trace length less than 10inch and keep skew on the differential pairs less than
20mil.
 The differential impedance of SGMII data trace is 100ohm±10%.
 To minimize crosstalk, the distance between separate adjacent pairs that are on the same layer must
be equal to or larger than 40mil.
For more information about SGMII application, please refer to document [5]and document[7].
NOTE