User's Manual

LTE Module Series
EC21 Hardware Design
EC21_Hardware_Design Confidential / Released 52 / 94
Table 21: Pin Definition of the SGMII Interface
Pin Name Pin No. I/O Description Comment
Control Signal Part
EPHY_RST_N 119 DO Ethernet PHY reset 1.8V/2.85V power domain
EPHY_INT_N 120 DI Ethernet PHY interrupt 1.8V power domain
SGMII_MDATA 121 IO
SGMII MDIO (Management Data
Input/Output) data
1.8V/2.85V power domain
SGMII_MCLK 122 DO
SGMII MDIO (Management Data
Input/Output) clock
1.8V/2.85V power domain
USIM2_VDD 128 PO
SGMII MDIO pull-up power
source
Configurable power source.
1.8V/2.85V power domain.
External pull-up power source for
SGMII MDIO pins.
SGMII Signal Part
SGMII_TX_M 123 AO SGMII transmission-minus
Connect with a 0.1uF capacitor,
close to the PHY side.
SGMII_TX_P 124 AO SGMII transmission-plus
Connect with a 0.1uF capacitor,
close to the PHY side.
SGMII_RX_P 125 AI SGMII receiving-plus
Connect with a 0.1uF capacitor,
close to EC21 module.
SGMII_RX_M 126 AI SGMII receiving-minus
Connect with a 0.1uF capacitor,
close to EC21 module.
The following figure shows the simplified block diagram for Ethernet application.
Module
AR8033
Ethernet
Transformer
RJ45
SGMII
Control
MDI
Figure 27: Simplified Block Diagram for Ethernet Application
The following figure shows a reference design of SGMII interface with PHY AR8033 application.