BG96 Hardware Design LTE Module Series Rev. BG96_Hardware_Design_V1.5 Date: 2017-05-31 www.quectel.
LTE Module Series BG96 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Office 501, Building 13, No.99, Tianzhou Road, Shanghai, China, 200233 Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/salesupport.
LTE Module Series BG96 Hardware Design About the Document History Revision Date Author Description 1.0 2017-01-05 Lyndon LIU/ Daryl DU/ Allen WANG Initial 1.1 2017-03-16 Allen WANG 1. 2. 1.2 1.3 2017-03-28 2017-04-11 Allen WANG/ Lyndon LIU Allen WANG 1. 2. 3. Updated function diagram in Figure 1. Updated pin assignment (top view) in Figure 2. Added the description of SPI interface in Chapter 3.12. 1. Updated model and frequency band of the module in Table1.
LTE Module Series BG96 Hardware Design Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index .......................................................................................................................................
LTE Module Series BG96 Hardware Design 3.12. 3.13. 3.14. 3.15. 3.16. SPI* Interface........................................................................................................................... 42 Network Status Indication ........................................................................................................ 43 STATUS ................................................................................................................................... 44 Behaviors of RI ........
LTE Module Series BG96 Hardware Design 11 Appendix C GPRS Multi-slot Classes .............................................................................................. 76 12 Appendix D EDGE Modulation and Coding Schemes ...................................................................
LTE Module Series BG96 Hardware Design Table Index TABLE 1: FREQUENCY BANDS OF BG96 MODULE ....................................................................................... 11 TABLE 2: KEY FEATURES OF BG96 ............................................................................................................... 13 TABLE 3: DEFINITION OF I/O PARAMETERS ................................................................................................. 19 TABLE 4: PIN DESCRIPTION ....................
LTE Module Series BG96 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 16 FIGURE 2: PIN ASSIGNMENT (TOP VIEW)..................................................................................................... 18 FIGURE 3: SLEEP MODE APPLICATION VIA UART .......................................................................................
LTE Module Series BG96 Hardware Design FIGURE 38: BOTTOM VIEW OF THE MODULE .............................................................................................. 69 FIGURE 39: REFLOW SOLDERING THERMAL PROFILE ..............................................................................
LTE Module Series BG96 Hardware Design 1 Introduction This document defines BG96 module and describes its air interface and hardware interfaces which are connected with customers’ applications. This document can help customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of BG96. To facilitate its application in different fields, reference design is also provided for customers’ reference.
LTE Module Series BG96 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating BG96. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product.
LTE Module Series BG96 Hardware Design 2 Product Concept 2.1. General Description BG96 is an embedded IoT (LTE Cat.M1) wireless communication module without receive diversity. It supports LTE-TDD and Half-Duplex LTE-FDD wireless communication, which provides data connectivity on LTE-TDD/FDD networks. It also provides GNSS1) function and voice2) interface to meet customers’ specific application demands. The following table shows the frequency bands of BG96 module.
LTE Module Series BG96 Hardware Design 2.2. Directives and Standards The BG96 module is designed to comply with the FCC statements. FCC ID: XMR201707BG96 The Host system using BG96 should have label “contains FCC ID: XMR201707BG96 2.2.1. FCC Statement According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met: 1. This Modular Approval is limited to OEM installation for mobile and fixed applications only.
LTE Module Series BG96 Hardware Design to the OEM the labeling requirements, options and OEM user manual instructions that are required (see next paragraph).
LTE Module Series BG96 Hardware Design Power Supply Supply voltage: 3.3V~4.3V Typical supply voltage: 3.8V LTE Features Support up to LTE Cat.M1 Support 1.08MHz RF bandwidth Support SISO in DL direction Cat.M1: Max. 375kbps (DL)/375kbps (UL) GSM Features GPRS: Support GPRS multi-slot class 12 (12 by default) Coding schemes: CS-1, CS-2, CS-3 and CS-4 Maximum of four Rx time slots per frame GPRS: Max. 85.6kbps (DL)/85.
LTE Module Series BG96 Hardware Design UART3 is the default configuration when the module is used as a modem. In this case, it is used for outputting GNSS data or NEMA sentences. When the module is used as the core board, the port can be multiplexed into SPI* interface for data transferring. AT Commands 3GPP TS 27.007 and 3GPP TS 27.
LTE Module Series BG96 Hardware Design ANT_GNSS ANT_MAIN Filter PA RF3628 VBAT_RF LNA PA RF5212A GNSS PRx Tx NAND DDR2 SDRAM Transceiver IQ VBAT_BB PMIC Control Control PWRKEY Baseband RESET_N STATUS 19.2M XO NETLIGHT VDD_EXT USB USIM I2S* UART/SPI* I2C GPIOs Figure 1: Functional Diagram NOTE “*” means under development. 2.5.
LTE Module Series BG96 Hardware Design 3 Application Interfaces BG96 is equipped with 62-pin 1.1mm pitch SMT pads and 40-pin ground/reserved pads that can be connected to customers’ cellular application platforms.
LTE Module Series BG96 Hardware Design 3.1. Pin Assignment The following figure shows the pin assignment of BG96.
LTE Module Series BG96 Hardware Design NOTES 1. 2. 3. 4. Keep all RESERVED pins and unused pins unconnected. GND pads should be connected to ground in the design. 1) PWRKEY output voltage is 0.8V because of the diode drop in the Qualcomm chipset. “*” means under development. 3.2. Pin Description The following tables show the pin definition and description of BG96.
LTE Module Series BG96 Hardware Design part Vnorm=3.8V Provide 1.8V for external circuit Vnorm=1.8V IOmax=50mA Power supply for external GPIO’s pull up circuits. Description DC Characteristics Comment DI Turn on/off the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V The output voltage is 0.8V because of the diode drop in the Qualcomm chipset. DI Reset signal of the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V If unused, keep this pin open.
LTE Module Series BG96 Hardware Design USB_DM 10 IO USB differential data bus (-) Compliant with USB 2.0 standard specification. Require differential impedance of 90Ω. I/O Description DC Characteristics Comment (U)SIM Card Interface Pin Name USIM_GND Pin No. Specified ground for (U)SIM card 47 For 1.8V (U)SIM: Vmax=1.9V Vmin=1.7V USIM_VDD 43 PO Power supply for (U)SIM card For 3.0V (U)SIM: Vmax=3.05V Vmin=2.7V Either 1.8V or 3V is supported by the module automatically.
LTE Module Series BG96 Hardware Design VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. 42 DI (U)SIM card insertion detection Pin Name Pin No. I/O Description DC Characteristics Comment RI 39 DO Ring indicator VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. DCD 38 DO Data carrier detection VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. 1.8V power domain. If unused, keep it open.
LTE Module Series BG96 Hardware Design GPIO/ SPI_CLK* 26 DO UART3_TXD/ SPI_MOSI* 27 DO GPIO/SPI master clock Transmit data/ Master Out Salve In of SPI interface VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. 28 DI Receive data/ Master In Slave Out of SPI interface Pin Name Pin No.
LTE Module Series BG96 Hardware Design ANT_MAIN 60 IO Main antenna interface 50Ω impedance ANT_GNSS 49 AI GNSS antenna interface 50Ω impedance If unused, keep it open. Pin No. I/O Description DC Characteristics Comment Power saving mode indicator VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. 1.8V power domain. Pull-up by default. In low voltage level, the module can enter into airplane mode. If unused, keep it open.
LTE Module Series BG96 Hardware Design RESERVED Pins Pin Name RESERVED Pin No. 11~14, 16, 25, 51, 56, 57, 65,66, 76~78, 83~88, 92~99 I/O Description DC Characteristics Reserved Comment Keep these pins unconnected. NOTES 1. Keep all RESERVED pins and unused pins unconnected. 2. “*” means under development. 3.3. Operating Modes The table below briefly summarizes the various operating modes referred in the following chapters.
LTE Module Series BG96 Hardware Design Power Down Mode In this mode, the power management unit shuts down the power supply. Software is not active. The serial interface is not accessible. Operating voltage (connected to VBAT_RF and VBAT_BB) remains applied. NOTES 1. 2. In PSM or sleep mode, it is recommended to use UART interface for module connection. USB connection is NOT recommended as it will cause increase in power consumption. “*” means under development. 3.4. Power Saving 3.4.1.
LTE Module Series BG96 Hardware Design Driving the host DTR to low level will wake up the module. When BG96 has URC to report, RI signal will wake up the host. Refer to Chapter 3.15 for details about RI behaviors. AP_READY* will detect the sleep state of the host (can be configured to high level or low level detection). Please refer to AT+QCFG=“apready” command for details. 3.4.1.2.
LTE Module Series BG96 Hardware Design The following figure shows the connection between the module and the host. Module Host VDD USB_VBUS USB_DP USB_DP USB_DM USB_DM AP_READY* GPIO RI EINT GND GND Figure 5: Sleep Mode Application with RI Sending data to BG96 through USB will wake up the module. When BG96 has a URC to report, RI signal will wake up the host. 3.4.1.4.
LTE Module Series BG96 Hardware Design Switching on the power switch to supply power to USB_VBUS will wake up the module. NOTES 1. 2. Please pay attention to the level match shown in dotted line between the module and the host. Refer to document [1] for more details about BG96 power management application. “*” means under development. 3.4.2. Airplane Mode When the module enters into airplane mode, the RF function does not work, and all AT commands correlative with RF function will be inaccessible.
LTE Module Series BG96 Hardware Design Table 6: VBAT and GND Pins Pin Name Pin No. Description Min. Typ. Max. Unit VBAT_RF 52, 53 Power supply for module’s RF part 3.3 3.8 4.3 V VBAT_BB 32, 33 Power supply for module’s baseband part 3.3 3.8 4.3 V GND 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 67~74, 79~82, 89~91, 100~102 Ground - - - - 3.5.2. Decrease Voltage Drop The power supply range of the module is from 3.3V to 4.3V.
LTE Module Series BG96 Hardware Design 3.5.3. Monitor the Power Supply AT+CBC command can be used to monitor the VBAT_BB voltage value. For more details, please refer to document [2]. 3.6. Turn on and off Scenarios 3.6.1. Turn on Module Using the PWRKEY Pin The following table shows the pin definition of PWRKEY. Table 7: Pin Definition of PWRKEY Pin Name PWRKEY Pin No. 15 Description DC Characteristics Comment Turn on/off the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V The output voltage is 0.
LTE Module Series BG96 Hardware Design S1 PWRKEY TVS Close to S1 Figure 9: Turn on the Module Using Keystroke The turn on scenario is illustrated in the following figure. NOTE VBAT ≥100ms VIH≥1.3V PWRKEY VIL≤0.5V RESET_N TBD STATUS (OD) TBD UART Inactive Active TBD USB Inactive Active Figure 10: Timing of Turning on Module NOTE Make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less than 30ms.
LTE Module Series BG96 Hardware Design 3.6.2. Turn off Module The following procedures can be used to turn off the module: Normal power down procedure: Turn off the module using the PWRKEY pin. Normal power down procedure: Turn off the module using AT+QPOWD command. 3.6.2.1. Turn off Module Using the PWRKEY Pin Driving the PWRKEY pin to a low level voltage (the specific time is TBD), the module will execute power-down procedure after the PWRKEY is released.
LTE Module Series BG96 Hardware Design 3.7. Reset the Module The RESET_N pin can be used to reset the module. The module can be reset by driving RESET_N to a low level voltage for time between 150ms and 460ms. Table 8: RESET_N Pin Description Pin Name RESET_N Pin No. Description DC Characteristics 17 Reset signal of the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Comment The recommended circuit is similar to the PWRKEY control circuit.
LTE Module Series BG96 Hardware Design VBAT ≤460ms ≥150ms RESET_N VIH≥1.3V VIL≤0.5V Module Status Running Resetting Restart Figure 14: Timing of Resetting Module NOTES 1. 2. Use RESET_N only when turning off the module by AT+QPOWD command and PWRKEY pin both failed. Ensure that there is no large capacitance on PWRKEY and RESET_N pins. 3.8. (U)SIM Card Interface The (U)SIM card interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8V and 3.0V (U)SIM cards are supported.
LTE Module Series BG96 Hardware Design BG96 supports (U)SIM card hot-plug via the USIM_PRESENCE pin. The function supports low level and high level detections, and is disabled by default. Please refer to document [2] about AT+QSIMDET command for details. The following figure shows a reference design of (U)SIM card interface with an 8-pin (U)SIM card connector.
LTE Module Series BG96 Hardware Design Figure 16: Reference Circuit of (U)SIM Card Interface with a 6-Pin (U)SIM Card Connector In order to enhance the reliability and availability of the (U)SIM card in applications, please follow the criteria below in (U)SIM circuit design: Keep layout of (U)SIM card as close to the module as possible. Keep the trace length as less than 200mm as possible. Keep (U)SIM card signals away from RF and VBAT traces.
LTE Module Series BG96 Hardware Design The USB interface is recommended to be reserved for firmware upgrade in your design. The following figure shows a reference circuit of USB interface.
LTE Module Series BG96 Hardware Design 3.10. UART Interfaces The module provides three UART interfaces: UART1, UART2 and UART3 interfaces. The following are their features. UART1 interface supports 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 and 3000000bps baud rates, and the default is 115200bps. This interface is used for data transmission and AT command communication. UART2 interface supports 115200bps baud rate. It is used for module debugging and log output.
LTE Module Series BG96 Hardware Design Table 13: Pin Definition of UART3 Interface Pin Name Pin No. I/O Description Comment UART3_TXD 27 DO Transmit data 1.8V power domain UART3_RXD 28 DI Receive data 1.8V power domain The logic levels are described in the following table. Table 14: Logic Levels of Digital I/O Parameter Min. Max. Unit VIL -0.3 0.6 V VIH 1.2 2.0 V VOL 0 0.45 V VOH 1.35 1.8 V The module provides 1.8V UART interface.
LTE Module Series BG96 Hardware Design Another example with transistor translation circuit is shown as below. The circuit design of dotted line section can refer to the circuit design of solid line section, in terms of both module input and output circuit designs, but please pay attention to the direction of connection. VDD_EXT MCU/ARM 4.7K VDD_EXT 1nF 10K Module RXD TXD RXD TXD 10K VCC_MCU 1nF 4.
LTE Module Series BG96 Hardware Design I2S_D0* 6 IO I2S data 0 1.8V power domain I2S_D1* 7 IO I2S data 1 1.8V power domain I2C_SCL 40 OD I2C serial clock Require external pull-up to 1.8V I2C_SDA 41 OD I2C serial data Require external pull-up to 1.8V The following figure shows a reference design of I2S* and I2C interfaces with an external codec IC. I2S_MCLK MCLK I2S_BCLK BCLK I2S_WCLK WCLK I2S_D0 ADC I2S_D1 DAC INP INN BIAS MICBIAS LOUTP I2C_SDA SDA Module 4.7K SCL 4.
LTE Module Series BG96 Hardware Design Table 16: Pin Definition of SPI* Interface Pin Name Pin No. I/O Description Comment SPI_CLK* 26 DO SPI master clock 1.8V power domain. SPI_MOSI* 27 DO Master Out Slave in of SPI interface 1.8V power domain SPI_MISO* 28 DI Master In Slave Out of SPI interface 1.8V power domain NOTE “*” means under development. 3.13. Network Status Indication BG96 provides one network indication pin: NETLIGHT.
LTE Module Series BG96 Hardware Design VBAT Module 2.2K 4.7K NETLIGHT 47K Figure 21: Reference Circuit of the Network Status Indicator 3.14. STATUS The STATUS pin is an open drain output for indicating the module’s operation status. It can be connected to a GPIO of DTE with a pulled up resistor, or as LED indication circuit as below. When the module is turned on normally, the STATUS will present a low state. Otherwise, the STATUS will present high-impedance state.
LTE Module Series BG96 Hardware Design 3.15. Behaviors of RI AT+QCFG=“risignaltype”,“physical” command can be used to configure RI behavior. No matter on which port URC is presented, URC will trigger the behavior of RI pin. NOTE URC can be outputted from UART port, USB AT port and USB modem port, through configuration via AT+QURCCFG command. The default port is USB AT port. The default behaviors of RI are shown as below. Table 20: Default Behaviors of RI State Response Idle RI keeps in high level.
LTE Module Series BG96 Hardware Design The following figure shows a reference circuit of USB_BOOT interface.
LTE Module Series BG96 Hardware Design 4 GNSS Receiver 4.1. General Description BG96 includes a fully integrated global navigation satellite system solution that supports Gen8C-Lite of Qualcomm (GPS, GLONASS, BeiDou/Compass, Galileo and QZSS). BG96 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default. By default, BG96 GNSS engine is switched off. It has to be switched on via AT command.
LTE Module Series BG96 Hardware Design Accuracy (GNSS) @open sky XTRA* enabled TBD s CEP-50 Autonomous @open sky TBD m NOTES 1. 2. 3. 4. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock.
LTE Module Series BG96 Hardware Design 5 Antenna Interfaces BG96 includes a main antenna interface and a GNSS antenna interface. The antenna interfaces have an impedance of 50Ω. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of main antenna interface is shown below. Table 23: Pin Definition of Main Antenna Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 60 IO Main antenna interface 50Ω impedance 5.1.2.
LTE Module Series BG96 Hardware Design B13 777~787 746~757 MHz B20 832~862 791~821 MHz B26 814~848.9 859~893.9 MHz B28 703~748 758~803 MHz B39 1880~1920 1880~1920 MHz 5.1.3. Reference Design of RF Antenna Interface A reference design of ANT_MAIN antenna pad is shown as below. A π-type matching circuit should be reserved for better RF performance, and the π-type matching components (R1/C1/C2) should be placed as close the antenna as possible. The capacitors are not mounted by default.
LTE Module Series BG96 Hardware Design Figure 25: Microstrip Line Design on a 2-layer PCB Figure 26: Coplanar Waveguide Line Design on a 2-layer PCB Figure 27: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) BG96_Hardware_Design Confidential / Released 51 / 71
LTE Module Series BG96 Hardware Design Figure 28: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use impedance simulation tool to control the characteristic impedance of RF traces as 50Ω. The GND pins adjacent to RF pins should not be hot welded, and should be fully connected to ground.
LTE Module Series BG96 Hardware Design Table 26: GNSS Frequency Type Frequency Unit GPS/Galileo/QZSS 1575.42±1.023 MHz GLONASS 1597.5~1605.8 MHz BeiDou 1561.098±2.046 MHz A reference design of GNSS antenna is shown as below. VDD GNSS Antenna 10R 0.1uF Module 47nH 100pF ANT_GNSS NM NM Figure 29: Reference Circuit of GNSS Antenna Interface NOTES 1. 2. An external LDO can be selected to supply power according to the active antenna requirement.
LTE Module Series BG96 Hardware Design 5.3. Antenna Installation 5.3.1. Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna. Table 27: Antenna Requirements Antenna Type Requirements LTE/GSM VSWR: ≤ 2 Gain (dBi): 1 Max Input Power (W): 50 Input Impedance (Ω): 50 Polarization Type: Vertical Cable Insertion Loss: < 1dB (LTE B5/B8/B12/B13/B20/B26/B28 GSM850/GSM900) Cable Insertion Loss: < 1.
LTE Module Series BG96 Hardware Design Figure 30: Dimensions of the UF.L-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the UF.L-R-SMT. Figure 31: Mechanicals of UF.
LTE Module Series BG96 Hardware Design The following figure describes the space factor of mated connector. Figure 32: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com. 5.3.3.
LTE Module Series BG96 Hardware Design Figure 33: RF Reference Schematic Diagram C1, R1 and C2 form a “PI” type matching circuit which is reserved for antenna optimization. By default, R1 is 0ohm while C1 and C2 are both Not Mounted (NM).
LTE Module Series BG96 Hardware Design 5.3.4. Coplanar Waveguide Structure Design The recommended coplanar waveguide structure is shown as Figure 2. Figure 34: Structure of Coplanar WG The factors which influence impedance include dielectric constant (usually 4.2~4.6, here is 4.4), dielectric height (H), RF trace width (W), the space between RF trace, the ground (S) and copper thickness (T). When T=0.
LTE Module Series BG96 Hardware Design 1.2mm 0.8mm 0.16mm 1.6mm 0.8mm 0.15mm 2mm 0.8mm 0.14mm If there are two layers, the TOP layer is the signal layer, and the BOTTOM layer is the reference ground, as shown in Figure 3. If there are 4 layers, the reference ground could be the second layer, the third layer or the fourth layer. If third layer is chosen, the second layer should be kept out and the width of keepout area should be at least five times of the trace width, as shown in Figure 4.
LTE Module Series BG96 Hardware Design 5.3.5. Coplanar WG PCB Layout Example and Guidelines Figure 38: An example of PCB layout There are 6 guidelines should be taken into account, as marked in the above figure: 1. Control corresponding W and S of 50 ohm coplanar waveguide. Use the common PCB as FR4 medium (dielectric constant is 4.2) and take copper clad of 35 um thickness as an example. Values of W and S for 50 ohm coplanar WG under different PCB structure is shown as Table 1.
LTE Module Series BG96 Hardware Design possible and its corresponding reference ground in the opposite layer is as integrated as possible, meanwhile ensure the two layer ground is connected by amount of ground hole. 6. Three components consist of PI type matching circuit shown as Figure 6. Place the pad to antenna as close as possible, as shown in Figure 6.
LTE Module Series BG96 Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 29: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 4.7 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 TBD A Peak Current of VBAT_RF 0 TBD A Voltage at Digital Pins -0.3 2.3 V 6.2.
LTE Module Series BG96 Hardware Design Parameter Description USB_VBUS USB detection Conditions Min. Typ. Max. Unit 3.0 5.0 5.25 V 6.3. Operation Temperature The operation temperature is listed in the following table. Table 31: Operation Temperature Parameter Min. Typ. Max. Unit Operation Temperature Range 1) -35 +25 +75 ºC Extended Temperature Range 2) -40 +85 ºC NOTES 1. 2. 1) Within operation temperature range, the module is 3GPP compliant.
LTE Module Series BG96 Hardware Design 6.6. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of BG96 module. Table 32: BG96 Conducted RF Receiving Sensitivity Frequency Primary Diversity SISO 3GPP LTE-FDD B1 TBD Not Supported TBD -102.7dBm LTE-FDD B2 TBD Not Supported TBD -100.3dBm LTE-FDD B3 TBD Not Supported TBD -99.3dBm LTE-FDD B4 TBD Not Supported TBD -102.3dBm LTE-FDD B5 TBD Not Supported TBD -100.
LTE Module Series BG96 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm. 7.1. Mechanical Dimensions of the Module 22.50±0.1 26.50±0.1 2.3±0.
LTE Module Series BG96 Hardware Design 22.50 7.45 0.92 0.92 7.15 1.10 1.95 0.55 1.10 1.66 1.50 5.10 1.00 1.70 8.50 0.85 26.50 1.90 1.10 0.85 1.00 1.70 0.70 0.50 1.15 1.00 1.70 0.55 1.50 40x1.0 62x0.7 62x1.15 40x1.
LTE Module Series BG96 Hardware Design 7.2. Recommended Footprint and Stencil Design 22.50 7.15 7.45 1.50 1.95 1.10 1.65 1.10 5.10 1.00 26.50 1.70 0.20 8.50 0.85 1.10 1.90 1.10 0.85 1.00 1.70 1.00 1.70 1.15 0.55 1.15 1.65 0.70 62x0.7 62x1.15 1.50 40x1.00 40x1.
LTE Module Series BG96 Hardware Design 22.50 7.15 7.45 1.50 1.95 1.10 1.65 1.10 5.10 1.00 26.50 1.70 0.20 8.50 0.85 1.10 1.90 1.10 0.85 1.00 1.70 1.65 0.70 1.00 1.70 1.15 1.15 0.55 62x0.7 62x1.15 1.50 40x1.00 40x1.00 Figure 42: Recommended Stencil Design (Top View) NOTES 1. 2. For easy maintenance of the module, please keep about 3mm between the module and other components in the host PCB. All Reserved pins MUST be kept open.
LTE Module Series BG96 Hardware Design 7.3. Design Effect Drawings of the Module Figure 43: Top View of the Module Figure 44: Bottom View of the Module NOTE These are design effect drawings of BG96 module. For more accurate pictures, please refer to the module that you get from Quectel.
LTE Module Series BG96 Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage BG96 is stored in a vacuum-sealed bag. The storage restrictions are shown as below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be: Mounted within 168 hours at the factory environment of ≤30ºC/60%RH. Stored at <10%RH. 3.
LTE Module Series BG96 Hardware Design It is suggested that the peak reflow temperature is 235~245ºC (for SnAg3.0Cu0.5 alloy). The absolute max reflow temperature is 260ºC. To avoid damage to the module caused by repeated heating, it is suggested that the module should be mounted after reflow soldering for the other side of PCB has been completed. Recommended reflow soldering thermal profile is shown below.
LTE Module Series BG96 Hardware Design 9 Appendix A References Table 33: Related Documents SN Document Name Remark [1] Quectel_BG96_Power_Management_Application_Note BG96 Power Management Application Note [2] Quectel_BG96_AT_Commands_Manual BG96 AT Commands Manual [3] Quectel_BG96_GNSS_AT_Commands_Manual BG96 GNSS AT Commands Manual [4] Quectel_RF_Layout_Application_Note RF Layout Application Note [5] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide Table 34: Term
LTE Module Series BG96 Hardware Design ESD Electrostatic Discharge FDD Frequency Division Duplex FR Full Rate GMSK Gaussian Minimum Shift Keying GSM Global System for Mobile Communications HR Half Rate HSPA High Speed Packet Access HSDPA High Speed Downlink Packet Access HSUPA High Speed Uplink Packet Access I/O Input/Output Inorm Normal Current LED Light Emitting Diode LNA Low Noise Amplifier LTE Long Term Evolution MIMO Multiple Input Multiple Output MO Mobile Originated M
LTE Module Series BG96 Hardware Design SISO Single Input Single Output SMS Short Message Service TDD Time Division Duplexing TX Transmitting Direction UL Uplink UMTS Universal Mobile Telecommunications System URC Unsolicited Result Code (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Lev
LTE Module Series BG96 Hardware Design 10 Appendix B GPRS Coding Schemes Table 35: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
LTE Module Series BG96 Hardware Design 11 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
LTE Module Series BG96 Hardware Design 12 Appendix D EDGE Modulation and Coding Schemes Table 37: EDGE Modulation and Coding Schemes Coding Schemes Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1: GMSK / 9.05kbps 18.1kbps 36.2kbps CS-2: GMSK / 13.4kbps 26.8kbps 53.6kbps CS-3: GMSK / 15.6kbps 31.2kbps 62.4kbps CS-4: GMSK / 21.4kbps 42.8kbps 85.6kbps MCS-1 GMSK C 8.80kbps 17.60kbps 35.20kbps MCS-2 GMSK B 11.2kbps 22.4kbps 44.8kbps MCS-3 GMSK A 14.
