Product Info

Transistor
c
3.12. P
C
EC25 provi
d
following m
o
 Primar
y
 Auxilia
r
In primary
m
edge; the P
1024 and2
0
In auxiliary
edge; while
128kHz PC
EC25 supp
theprimary
auxiliary m
o
NOTE
E
MCU/
A
c
ircuit soluti
o
C
M and I
2
d
es one Pu
o
des:
y
mode (sh
o
r
y mode (lo
n
m
ode, the d
CM_SYNC
0
48kHz for
d
mode, the
d
the PCM_
S
M_CLK an
d
orts 8-bit
A
mode’s ti
m
o
de’s timing
E
C25-A_U
s
A
RM
/TXD
/RXD
/RTS
/CTS
GPIO
GPIO
EINT
GND
Figure 2
1
o
n is not sui
t
2
C Interf
a
lse Code M
o
rt sync, wo
r
n
g sync, wo
r
ata is sam
p
falling edge
d
ifferent spe
d
ata is sam
p
S
YNC rising
d
an 8kHz,
5
A
-law andμ-l
m
ing relatio
n
relationshi
p
s
e
r
_Manual
C
10K
VCC_MCU
VDD_EXT
1
: Referenc
t
able for hig
a
ce
odulation (
P
r
ks as both
r
ks as mast
e
p
led on the
f
represents
ech codecs
p
led on the
f
edge repre
s
5
0% duty cy
c
aw, and al
s
n
ship with
8
p
with 8kHz
C
onfidenti
a
V
4.7K
4.7K
1nF
1nF
e Circuit w
i
h baud rate
P
CM) digital
master and
e
r only)
f
alling edge
the MSB. I
n
.
f
alling edge
s
ents the M
S
c
le PCM_S
Y
s
o 16-bit li
n
8
kHz PCM
_
PCM_SYN
C
a
l / Release
V
DD_EXT
10K
VDD_EXT
i
th Transis
t
s exceedin
g
interface f
o
slave)
of the PC
M
n
this mode,
of the PC
M
S
B. In this
m
Y
NC only.
n
ear data f
o
_
SYNC an
d
C
and 128k
H
d 38 /
6
TXD
RXD
RTS
CTS
DTR
RI
GND
DCD
M
o
t
or Circuit
g
460Kbps.
o
r audio de
s
M
_CLK and
t
PCM_CLK
M
_CLK and
t
m
ode, PCM i
o
rmats. The
d
2048kHz
H
z PCM_C
L
L
EC25-AU
6
9
o
dule
s
ign, which
s
t
ransmitted
o
supports 1
2
t
ransmitted
nterface op
e
following
f
PCM_CLK,
L
K.
L
TE Modul
e
ser Manu
a
s
upports th
e
o
n the risin
g
2
8, 256, 51
2
on the risin
g
e
rates with
a
igures sho
w
as well a
s
e
a
l
e
g
2
,
g
a
w
s