User's Manual

UMTS/HSPA Module Series
UG96 Hardware Design
UG96_Hardware_Design Confidential / Released 22 / 75
PCM_SYNC
5
DO
PCM data frame
sync signal.
V
OL
max=0.25V
V
OH
min=1.55V
1.8V power domain.
In master mode, it is
an output signal.
If unused, keep this
pin open.
PCM_CLK
4
DO
PCM data bit clock.
V
OL
max=0.25V
V
OH
min=1.55V
1.8V power domain.
In master mode, it’s
an output signal.
If unused, keep this
pin open.
I2C Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
I2C_SCL
40
OD
I2C serial clock.
1.8V power domain.
External pull-up
resistor is required.
If unused, keep this
pin open.
I2C_SDA
41
OD
I2C serial data.
1.8V power domain.
External pull-up
resistor is required.
If unused, keep this
pin open.
Other Pins
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
AP_READY
19
DI
Application
processor sleep
state detection.
V
IL
min=-0.3V
V
IL
max=0.35V
V
IH
min=1.3V
V
IH
max=1.85V
1.8V power domain.
If unused, keep this
pin open.
CLK_OUT
25
DO
Clock output.
Provide a digital clock
output for an external
audio codec.
If unused, keep this
pin open.
RESERVED Pins
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
RESERVED
1, 2,
11~14,
18,
22~24,
26~28,
Reserved
Keep these pins
unconnected.