User's Manual

UMTS/HSPA Module Series
UG95 Hardware Design
UG95_Hardware_Design Confidential / Released 44 / 67
details. Data bit is 32 bit and the sampling rate is 8 KHz. The following figure shows the timing of the
application with ALC5616 codec.
PCM_CLK
PCM_SYNC
PCM_IN/OUT
32
1 0
31
Sampling freq. = 8 KHz
32-bit data word
BCLK = 264 KHz
33
MSB
Figure 26: PCM Master Mode Timing
In general, the BitClockFrequency (CLK) is furnished by the following expression:
BitClockFrequency = (DataWordBit +1) × SamplingFrequency
The following figure shows the reference design of PCM interface with external codec IC.
PCM_IN
PCM_OUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
CODEC
Module
1.8V
1K
1K
BCLK
LRCLK
DACDAT
ADCDAT
SCL
SDA
BIAS
MICBIAS
MIC+
MIC-
SPK+
SPK-
Figure 27: Reference Circuit of PCM Application with Audio Codec
It is recommended to reserved RC (R=22Ω, C=22pF) circuit on the PCM lines, especially for PCM_CLK.
NOTE