User's Manual
UMTS/HSPA Module Series
UG95 Hardware Design
UG95_Hardware_Design Confidential / Released 32 / 67
Reset pulse
RESET_N
4.7K
47K
≥ 100ms
Figure 13: Reference Circuit of RESET_N by Using Driving Circuit
RESET_N
S3
Close to S3
TVS
Figure 14: Reference Circuit of RESET_N by Using Button
The reset scenario is illustrated as the following figure.
V
IL
≤ 0.5V
V
IH
≥ 1.3V
VBAT
≥ 100ms
RESTARTING
Module
Status
RESET_N
RUNNING
> 5s
STATUS
> 3s
RUNNING
OFF
Figure 15: Timing of Resetting Module