M50Hardware Design M50 Quectel Cellular Engine Hardware Design M50_HD_V2.0 M50_HD_V2.
M50Hardware Design Document Title M50 Hardware Design Revision 2.0 Date 2012-06-26 Status Released Document Control ID M50_HD_V2.0 l te General Notes Quectel offers this information as a service to its customers, to support application and engineering efforts that use the products designed by Quectel. The information provided is based upon requirements specifically provided for customers of Quectel.
M50Hardware Design Contents Contents ................................................................................................................................................... 3 Table Index .............................................................................................................................................. 5 Figure Index ............................................................................................................................................ 6 0.
M50Hardware Design 3.10.3. Receiver and speaker interface design ...................................................................... 52 3.10.4. Earphone interface design.......................................................................................... 54 3.10.5. Loud speaker interface design ................................................................................... 54 3.10.6. Audio characteristics ..........................................................................................
M50Hardware Design Table Index TABLE 1: RELATED DOCUMENTS ..................................................................................................... 9 TABLE 2: TERMS AND ABBREVIATIONS........................................................................................ 10 TABLE 3: MODULE KEY FEATURES ................................................................................................ 15 TABLE 4: CODING SCHEMES AND MAXIMUM NET DATA RATES OVER AIR INTERFACE ..
M50Hardware Design Figure Index FIGURE 1: MODULE FUNCTIONAL DIAGRAM ............................................................................. 18 FIGURE 2: PIN ASSIGNMENT ............................................................................................................ 20 FIGURE 3: VOLTAGE RIPPLE DURING TRANSMITTING ............................................................. 30 FIGURE 4: REFERENCE CIRCUIT FOR THE VBAT INPUT ............................................................
M50Hardware Design FIGURE 42: REFERENCE DESIGN FOR PCM .................................................................................. 64 FIGURE 43: RI BEHAVIOR OF VOICE CALLING AS A RECEIVER .............................................. 67 FIGURE 44: RI BEHAVIOR OF DATA CALLING AS A RECEIVER ................................................ 67 FIGURE 45: RI BEHAVIOR AS A CALLER ........................................................................................
M50Hardware Design 0. Revision history Revision Date Author Description of change 1.0 2011-12-20 Ray XU Initial 1.1 2012-02-03 Ray XU 1. Updated PCM interface 2. Updated SD interface 3. Updated charging interface l te 4. Updated timing of turning on the module 1.2 2012-07-20 Baly BAO 1. Deleted the USB interface 2. Deleted the camera interface 1.3 2012-10-22 Mountain ZHOU 1. Updated functional diagram 2. Updated reference design circuit 3.
M50 Hardware Design 1. Introduction This document defines the M50 module and describes the hardware interface of M50 which are connected with the customer application and the air interface. This document can help customers quickly understand module interface specifications, electrical and mechanical details. Associated with application notes and user guide, customers can use M50module to design and set up mobile applications easily. 1.1.
M50 Hardware Design 1.2.
M50 Hardware Design Li-Ion Lithium-Ion MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PBCCH Packet Switched Broadcast Control Channel PCB Printed Circuit Board PDU Protocol Data Unit PPP Point-to-Point Protocol RF Radio Frequency RMS Root Mean Square (value) RTC Real Time Clock RX Receive Direction Subscriber Identification Module SMS Short Message Service TDMA Time Division Multiple Access TE Terminal Equipment
M50 Hardware Design 1.3. Safety cautions The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating M50module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel and to incorporate these guidelines into all manuals supplied with the product.
M50 Hardware Design GSM cellular terminals or mobiles operate over radio frequency signal and cellular network and cannot be guaranteed to connect in all conditions, for example no mobile fee or an invalid SIM card. While you are in this condition and need emergent help, Please Remember using emergency call. In order to make or receive call, the cellular terminal or mobile must be switched on and in a service area with adequate cellular signal strength.
M50 Hardware Design The manual of the host system, which uses M50, must include RF exposure warning statement to advice user should keep minimum 20cm from the radio antenna of M50 module depending on the Mobile status. The following list of antenna is indicating the maximum permissible antenna gain. Type External Antenna Internal Antenna Maximum Gain Maximum Gain (850Hz/900Hz) (1800Hz/1900Hz) Monopole 0.5dBi 2dBi Vehicular antenna 0.5dBi 2dBi Monopole 0.5dBi 2dBi PIFA 0.5dBi 2dBi FPC 0.
M50 Hardware Design 2. Product concept M50 is a Quad-band GSM/GPRS engine that works at frequencies of GSM850MHz, GSM900MHz, DCS1800MHz and PCS1900MHz. The M50 features GPRS multi-slot class 12 and supports the GPRS coding schemes CS-1, CS-2, CS-3 and CS-4. For more details about GPRS multi-slot classes and coding schemes, please refer to the Appendix A and Appendix B. With a tiny profile of 24.5mm×25.3mm ×2.
M50 Hardware Design Temperature range DATA GPRS: CSD: Normal operation: -35°C ~ +80°C Restricted operation: -40°C ~ -35°C and +80°C ~ +85°C 1) Storage temperature: -45°C ~ +90°C GPRS data downlink transfer: max. 85.6 kbps GPRS data uplink transfer: max. 85.
M50 Hardware Design Antenna interface Connected to antenna pad with 50 Ohm impedance control 1）When the module works in this temperature range, the deviations from the GSM specification may occur. For example, the frequency error or the phase error will be increased. Table 4: Coding schemes and maximum net data rates over air interface Coding scheme 1 Timeslot 2 Timeslot CS-1 9.05kbps 18.1kbps CS-2 13.4kbps 26.8kbps CS-3 15.6kbps 31.2kbps CS-4 21.4kbps 42.8kbps 4 Timeslot l te 36.
M50 Hardware Design RF_ANT ESD SAW Filter RF PAM VBAT Charge Interface 26MHz RF Transceiver Charge PWRKEY Reset EMERG_OFF VRTC RTC PMU 32KHz SIM Interface SIM Interface BB&RF l te SD Interface SD Interface PCM Interface PCM Inteface c l c a i e t u n Q fide n o C STATUS& NETLIGHT GPIO UART Serial Interface Memory Interface ADC ADC Audio Audio Serial Flash Figure 1: Module functional diagram 2.3.
M50 Hardware Design 3. Application interface The module is equipped with 83-pin SMT pads and it adopts LCC package. Detailed descriptions on Sub-interfaces included in these pads are given in the following chapters: Power supply Power on/down Charge interface RTC Serial interfaces Audio interfaces SIM interface SD interface PCM interface ADC l te c l c a i e t u n Q fide n o C M50_HD_V2.
M50 Hardware Design 3.1. Pin of module SIM_PRESENCE RESERVED l te VRTC GND VDD_EXT GND RF_ANT GND GND VBAT GND VBAT VBAT VBAT RESERVED RESERVED RESERVED RESERVED 3.1.1.
M50 Hardware Design Table 5: M50 pin assignment 管脚号 管脚名 输入/输出 管脚号 管脚名 输入/输出 1 ADC1 I 2 ADC0 I 3 RESERVED 4 NETLIGHT O 5 SPK2P O 6 AGND 7 MIC2P I 8 MIC2N I 9 MIC1P I 10 MIC1N I 11 SPK1N O 12 SPK1P O 13 LOUDSPKN O 14 LOUDSPKP O 15 STATUS O 16 PWRKEY I 17 EMERG_OFF I 18 PCM_IN I 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 l te c l c a i e t u n Q fide n o C PCM_CLK O 20 PCM_OUT PCM_SYNC O 22 RESERVED RESERVED 24 RES
M50 Hardware Design 73 RESERVED 74 RESERVED 75 RESERVED 76 RESERVED 77 RESERVED 78 RESERVED 79 GND 80 GND 81 GND 82 GND 83 GND Note: Keep all reserved pins open. 3.1.2. Pin description Table 6: Pin description l te c l c a i e t u n Q fide n o C Power supply PIN NAME PIN NO. I/O DESCRIPTION DC CHARACTERISTICS COMMENT VBAT 67, 68, 69， I Main power supply of module: VBAT=3.3V~4.6V Vmax= 4.6V Vmin=3.3V Vnorm=4.
M50 Hardware Design 62, 64, 65, 66, Turn on/off PIN NAME PIN NO. I/O DESCRIPTION DC CHARACTERISTICS COMMENT PWRKEY 15 I Turn on/off control. PWRKEY should be pulled down for a VILmax= 0.1×VBAT VIHmin= Pulled up to VBAT internally. moment to turn on or off the system. 0.6×VBAT VImax=VBAT Emergency shutdown l te c l c a i e t u n Q fide n o C PIN NAME PIN NO. I/O DESCRIPTION DC CHARACTERISTICS COMMENT EMERG_OFF 17 I Emergency off. Pulled down for at least 20ms, which VILmax=0.
M50 Hardware Design MIC2P 7, 8 I MIC2N SPK1P SPK1N Channel two for positive and negative voice-band input 12, 11 SPK2P 5 AGND 6 O O Channel one for positive and negative voice-band 1. If unused, keep these pins open. output 2. Support both voice and ringtone output. Channel two for voice-band output l te Analog ground. Constitute a pseudo differential channel c l c a i e t u n Q fide n o C with SPK2P. LOUDSPKN 13, LOUDSPKP 14 O Channel three of 1.
M50 Hardware Design 0.15×VDD_EXT Debug Port PIN NAME PIN I/O DESCRIPTION NO. DBG_TXD 42 DC COMMENT CHARACTERISTICS O UART interface for debugging only. VILmin=0V VILmax= If unused, keep these pins open. 0.25×VDD_EXT VIHmin= 0.75×VDD_EXT DBG_RXD 43 I l te VIHmax= VDD_EXT+0.3 VOHmin= c l c a i e t u n Q fide n o C 0.85×VDD_EXT VOLmax= 0.15×VDD_EXT Auxiliary UART Port PIN NAME PIN I/O DESCRIPTION NO.
M50 Hardware Design 0.15×SIM_VDD holder. VOHmin= SIM_VDD-0.4 SIM_CLK 55 O SIM clock 3V： VOLmax=0.4 VOHmin= 0.9×SIM_VDD 1.8V: VOLmax= 0.12×SIM_VDD l te VOHmin= 0.9×SIM_VDD SIM_RST 53 O SIM reset 3V： c l c a i e t u n Q fide n o C VOLmax=0.36 VOHmin= 0.9×SIM_VDD 1.8V: VOLmax= 0.2×SIM_VDD VOHmin= 0.9×SIM_VDD SIM_GND 52 SIM_PRESEN CE 57 SIM ground I SIM card detection VILmin=0V VILmax= If unused, keep this pin open. 0.25×VDD_EXT VIHmin= 0.75×VDD_EXT VIHmax= VDD_EXT+0.
M50 Hardware Design PCM_OUT 20 O PCM data output PCM_SYNC 21 O PCM frame synchronization 0.25×VDD_EXT VIHmin= 0.75×VDD_EXT VIHmax= VDD_EXT+0.3 VOHmin= 0.85×VDD_EXT VOLmax= 0.15×VDD_EXT l te SD card PIN NAME PIN NO. I/O DESCRIPTION DC CHARACTERISTICS SD_CMD 34 O SD command VILmin=0V COMMENT c l c a i e t u n Q fide n o C SD_CLK 35 O SD clock SD_DATA0 36 I/O SD data VILmax= 0.25×VDD_EXT VIHmin= 0.75×VDD_EXT VIHmax= VDD_EXT+0.3 VOHmin= 0.85×VDD_EXT VOLmax= 0.
M50 Hardware Design 71~ 75 l te c l c a i e t u n Q fide n o C M50_HD_V2.
M50 Hardware Design 3.2. Operating modes The table below briefly summarizes the various operating modes in the following chapters. Table 7: Overview of operating modes Mode Function Normal operation GSM/GPRS SLEEP The module will automatically go into SLEEP mode if DTR is set to high level and there is no interrupt (such as GPIO l te interrupt or data on UART port). In this case, the current consumption of module will reduce to the minimal level.
M50 Hardware Design 1) Use the EMERG_OFF pin only while failing to turn off the module by the command “AT+QPOWD=1” and the PWRKEY pin. Please refer to the Section 3.4.2.4. 3.3. Power supply 3.3.1. Power features of module The power supply is one of the key issues in the designing GSM terminals. Due to the 577us radio l te burst emission in GSM every 4.615ms, power supply must be able to deliver high current peaks in a burst period.
M50 Hardware Design VBAT + C1 C3 C4 10pF 33pF 0603 0603 C2 100uF 100nF l te GND Figure 4: Reference circuit for the VBAT input c l c a i e t u n Q fide n o C 3.3.3. Reference design for power supply The power design for the module is very important, since the performance of power supply for the module largely depends on the power source. The power supply is capable of providing the sufficient current up to 2A at least.
M50 Hardware Design 3.3.4. Monitor power supply To monitor the supply voltage, customer can use the “AT+CBC” command which includes three parameters: charging status, remaining battery capacity and voltage value (in mV). It returns the 0~100 percent of battery capacity and actual value measured between VBAT and GND. The voltage is automatically measured in period of 5s. The displayed voltage (in mV) is averaged over the last measuring period before the “AT+CBC” command is executed.
M50 Hardware Design The other way to control the PWRKEY is using a button directly. A TVS component is indispensable to be placed nearby the button for ESD protection. When pressing the key, electrostatic strike may generate from finger. A reference circuit is shown in the following figure. S1 PWRKEY TVS1 Close to S1 l te c l c a i e t u n Q fide n o C Figure 7: Turn on the module using keystroke The power-on scenarios is illustrated as the following figure.
M50 Hardware Design 3.4.2. Power down The following procedures can be used to turn off the module: Normal power down procedure: Turn off module using the PWRKEY pin Normal power down procedure: Turn off module using command “AT+QPOWD” Over-voltage or under-voltage automatic shutdown: Take effect when over-voltage or under-voltage is detected Emergent power down procedure: Turn off module using the EMERG_OFF pin 3.4.2.1.
M50 Hardware Design STATUS pin, which is a low level voltage in this mode. 3.4.2.2. Power down module using AT command Customer’s application can turn off the module via AT command “AT+QPOWD=1”. This command will let the module to log off from the network and allow the firmware to save important data before completely disconnecting the power supply, thus it is a safe way.
M50 Hardware Design correctly synchronized after start-up. The module is recommended to set to a fixed baud rate. After that moment, no further AT commands can be executed. The module logs off from network and enters power down mode, and only RTC is still active. The power down mode can also be indicated by the pin STATUS, which is a low level voltage in this mode. 3.4.2.4.
M50 Hardware Design least 500ms should be delayed after detecting the low level of STATUS. The restart timing is illustrated as the following figure. Turn off PWRKEY (INPUT) Delay >0.5s Restart Pull down the PWRKEY to turn on the module STATUS (OUTPUT) l te c l c a i e t u n Q fide n o C Figure 12: Timing of restarting system The module can also be restarted by the PWRKEY after emergency shutdown.
M50 Hardware Design 3.5. Charge interface M50 provides charging function for rechargeable Li-Ion or Lithium Polymer battery. It is introduced simply in this document. If customer wants to get more information about charging, please refer to the document [13]. Table 8: Pin definition of the charging l te Name Pin I/O Description.
M50 Hardware Design “AT+CFUN=1”. For detailed information about “AT+CFUN”, please refer to the document [1]. 3.6.2. SLEEP mode The SLEEP mode is disabled in default firmware configuration. Customer’s application can enable this mode by “AT+QSCLK=1”. On the other hand, the default setting is “AT+QSCLK=0” and in this mode, the module cannot enter SLEEP mode. l te When “AT+QSCLK=1” is sent to the module, customer’s application can control the module to enter or exit from the SLEEP mode through pin DTR.
M50 Hardware Design 3.8. RTC backup The RTC (Real Time Clock) can be supplied by an external capacitor or battery (rechargeable or non-chargeable) through the pin VRTC. A 1.5K resistor has been integrated in the module for current limiting. A coin-cell battery or a super-cap can be used to backup power supply for RTC. The following figures show various sample circuits for RTC backup. l te Module VRTC 1.
M50 Hardware Design Coin-type rechargeable capacitor such as XH414H-IV01E from Seiko can be used. l te c l c a i e t u n Q fide n o C Figure 17: Seiko XH414H-IV01E Charge Characteristics 3.9. Serial interfaces The module provides three serial ports: UART Port, Debug Port and Auxiliary UART Port. The module is designed as a DCE (Data Communication Equipment), following the traditional DCE-DTE (Data Terminal Equipment) connection. Autobauding function supports baud rate from 4800bps to 115200bps.
M50 Hardware Design The Debug Port DBG_TXD: Send data to the COM port of computer. DBG_RXD: Receive data from the COM port of computer. The Auxiliary UART Port TXD_AUX: Send data to the RXD of DTE. RXD_AUX: Receive data from the TXD of DTE. The logic levels are described in the following table. Table 10: Logic levels of the UART interfaces Parameter Min Max VIL 0 0.25×VDD_EXT 0.75×VDD_EXT VDD_EXT +0.3 VIH VOL VOH l te Unit c l c a i e t u n Q fide n o C 0.15×VDD_EXT 0.
M50 Hardware Design Used for AT command, GPRS data, etc. Multiplexing function is supported on the UART Port. So far only the basic mode of multiplexing is available. Support the communication baud rates as the following: 300, 600, 1200, 2400, 4800, 9600, 14400, 19200, 28800, 38400, 57600, 115200. The default setting is autobauding mode. Support the following baud rates for Autobauding function: 4800, 9600, 19200, 38400, 57600, 115200. The module disables hardware flow control by default.
M50 Hardware Design 3.9.1.2. The connection of UART The connection between module and host using UART Port is very flexible. Three connection styles are illustrated as below. Reference design for Full-Function UART connection is shown as below when it is applied in modulation-demodulation.
M50 Hardware Design UART Port with hardware flow control is shown as below. This connection will enhance the reliability of the mass data communication. Module (DCE) Host (DTE) Controller TXD TXD RXD RXD RTS RTS CTS CTS l te c l c a i e t u n Q fide n o C GND GND Figure 20: Reference design for UART Port with hardware flow control 3.9.1.3. Firmware upgrade The TXD, RXD can be used to upgrade firmware. The PWRKEY pin must be pulled down before the firmware upgrade.
M50 Hardware Design 3.9.2. Debug Port Debug Port Two lines: DBG_TXD and DBG_RXD It outputs log information automatically. Debug Port is only used for firmware debugging and its baud rate must be configured as 460800bps. Module (DCE) Debug port DBG_TXD l te Computer TXD c l c a i e t u n Q fide n o C DBG_RXD GND RXD GND Figure 22: Reference design for Debug Port 3.9.3.
M50 Hardware Design Host (DTE) Controller Module (DCE) TXD_AUX TXD RXD_AUX RXD GND GND l te Figure 23: Reference design for Auxiliary UART port c l c a i e t u n Q fide n o C 3.9.4. UART application The reference design of 3.3V level match is shown as below. If the host is a 3V system, please change the 5.6K resistor to 15K. Module MCU/ARM /TXD /RXD /RTS /CTS GPIO EINT GPIO 1K RXD 1K TXD 1K RTS 1K CTS 1K DTR 1K RI 1K DCD GND GND 5.6K 5.6K 5.6K Voltage level:3.
M50 Hardware Design The reference design for 5V level match is shown as below. The connection of dotted line can be referred to the connection of solid line. Please pay attention to the direction of signal. Input dotted line of module should be referred to input solid line of the module. Output dotted line of module should be referred to output solid line of the module. As to the circuit below, VDD_EXT supplies power for the I/O of module, while VCC_MCU supplies power for the I/O of the MCU/ARM. 4.
M50 Hardware Design The following circuit shows a reference design for the communication between module and PC. Since the electrical level of module is 2.8V, so a RS-232 level shifter must be used.
M50 Hardware Design 3.10. Audio interfaces The module provides two analogy input channels and three analogy output channels.
M50 Hardware Design Table 13: AOUT3 output characteristics Parameter Condition RMS power 8ohm Min load Typ Max Unit 800 mW 700 mW VBAT=4.3V THD+N=1% 8ohm load VBAT=3.7V THD+N=1% Gain adjustment range 0 Gain adjustment steps l te 18 3 dB dB c l c a i e t u n Q fide n o C 3.10.1. Decrease TDD noise and other noise The 33pF capacitor is applied for filtering out 900MHz RF interference when the module is transmitting at GSM900MHz. Without placing this capacitor, TDD noise could be heard.
M50 Hardware Design Close to Microphone GND GND GND Differential layout 33pF 0603 10pF 0603 ESD Electret Microphone MICxP 33pF 0603 10pF 0603 Module MICxN l te 33pF 0603 10pF 0603 ESD c l c a i e t u n Q fide n o C GND GND GND Figure 27: Reference design for AIN1&AIN2 3.10.3.
M50 Hardware Design Close to Speaker GND Differential layout SPK2P Module 33pF 0603 10pF 0603 ESD 22uF AGND l te c l c a i e t u n Q fide n o C Figure 29: Handset interface design for AOUT2 Close to Speaker GND Differential layout Amplifier circuit 10pF 0603 33pF 0603 10pF 0603 33pF 0603 ESD C1 SPK2P Module AGND C2 ESD GND Figure 30: Speaker interface design with an amplifier for AOUT2 Texas Instrument’s TPA6205A1is recommended for a suitable differential audio amplifier.
M50 Hardware Design 3.10.4. Earphone interface design Close to Socket Differential layout GND GND GND 4.7uF 33pF 0603 10pF 0603 MIC2N MIC2P 68R Module 22uF SPK2P ESD l te 3 AGND 33pF 0603 10pF 0603 4 2 1 c l c a i e t u n Q fide n o C ESD Amphenol 9001-8905-050 AGND AGND GND GND GND Figure 31: Earphone interface design 3.10.5.
M50 Hardware Design 3.10.6. Audio characteristics Table 14: Typical electret microphone characteristics Parameter Min Typ Max Unit Working Voltage 1.2 1.5 2.0 V Working Current 200 500 uA External Microphone Load Resistance 2.2 Table 15: Typical speaker characteristics Parameter Min Typ Load Resistance 28 32 Ref level 0 Load 28 kOhm l te Max Unit c l c a i e t u n Q fide n o C Normal Output Single Ended (AOUT1) Differential 2.
M50 Hardware Design Table 16: Pin definition of the SIM interface Name Pin Description SIM_VDD 56 Supply power for SIM Card. Automatic detection of SIM card voltage. 3.0V±10% and 1.8V±10%. Maximum supply current is around 10mA.
M50 Hardware Design Note: Please do not use “AT+QSIMDET=1,1” which causes to initialize SIM card when Figure 33 circuit is adopted. If customer does not need the SIM card detection function, keep SIM_PRESENCE open. The reference circuit using a 6-pin SIM card socket is illustrated as the following figure.
M50 Hardware Design l te c l c a i e t u n Q fide n o C Figure 35: Amphenol C707 10M006 512 2 SIM card holder Table 17: Pin description of Amphenol SIM card holder Name Pin Description SIM_VDD C1 SIM Card Power Supply SIM_RST C2 SIM Card Reset SIM_CLK C3 SIM Card Clock GND C5 Ground VPP C6 Not Connect SIM_DATA C7 SIM Card data I/O 3.11.3. 8 Pin SIM cassette For 8-pin SIM card holder, it is recommended to use Molex 91228. Please visit http://www.molex.com for more information.
M50 Hardware Design l te c l c a i e t u n Q fide n o C Figure 36: Molex 91228 SIM card holder Table 18: Pin description of Molex SIM card holder Name Pin Description SIM_VDD C1 SIM Card Power supply SIM_RST C2 SIM Card Reset SIM_CLK C3 SIM Card Clock SIM_PRESENCE C4 SIM Card Presence Detection GND C5 Ground VPP C6 Not Connect SIM_DATA C7 SIM Card Data I/O SIM_DETECT C8 Pulled down GND with external circuit. When the tray is present, C4 is connected to C8. M50_HD_V2.
M50 Hardware Design 3.12. SD card interface The module provides SD card interface that support many types of memory, such as Memory Stick, SD/MCC card and T-Flash or Micro SD card. The following are the main features of SD card interface. Only supports 1bit serial mode. Does not support the SPI mode SD/MMC memory card. Does not support hot plug. Up to 26MHz data rate in serial mode. Up to 32GB maximum memory card capacity.
M50 Hardware Design Table 20: Pin name of the SD card and Micro SD card Pin NO. Pin name of SD card Pin name of T-Flash(Micro SD) card 1 CD/DATA3 DATA2 2 CMD CD/DATA3 3 VSS1 CMD 4 VDD VDD 5 CLK CLK 6 VSS2 VSS 7 DATA0 DATA0 8 DATA1 DATA1 9 DATA2 l te c l c a i e t u n Q fide n o C In SD card interface designing, in order to ensure good communication performance with SD card, the following design principles should be complied with. Route SD card trace as short as possible.
M50 Hardware Design 3.13. PCM interface M50 supports PCM interface. It is used for digital audio transmission between the module and the customer’s device. This interface is composed of PCM_CLK, PCM_SYNC, PCM_IN and PCM_OUT signal lines. Pulse-code modulation (PCM) is a converter that changes the consecutive analog audio signal to discrete digital signal. The whole procedure of Pulse-code modulation contains sampling, quantizing and encoding.
M50 Hardware Design 3.13.2. Timing The sample rate of the PCM interface is 8 KHz and the clock source is 256 KHz, so every frame contains 32 bits data, since M50 supports 16 bits line code PCM format, the left 16 bits are invalid. The following diagram shows the timing of different combinations. The synchronization length in long synchronization format can be programmed by firmware from one bit to eight bits.
M50 Hardware Design PCM_CLK PCM_SYNC MSB PCM_OUT 12 11 10 9 8 7 6 5 4 3 2 1 0 Zero padding 9 8 7 6 5 4 3 2 1 0 Zero padding MSB PCM_IN 12 11 10 l te Figure 41: Short synchronization & Zero padding diagram c l c a i e t u n Q fide n o C 3.13.3. Reference design As M50 only acts as a master, the module provides synchronization and clock source. The reference design is shown as below.
M50 Hardware Design Table 23: QPCMON command description Parameter scope Description Mode 0~2 0: Close PCM 1: Open PCM 2: Open PCM when audio talk is set up Sync_Type 0~1 0: Short synchronization 1: Long synchronization Sync_Length 1~8 Programmed from one bit to eight bit SignExtension 0~1 0: Zero padding 1: Sign extension MSBFirst 0~1 0: MSB first l te 1: Not supported c l c a i e t u n Q fide n o C “AT+QPCMVOL” can configure volume of input and output.
M50 Hardware Design 3.14. ADC The module provides two ADC channel to measure the value of voltage. Please give priority to the use of ADC0 channel. The command “AT+QADC” can read the voltage value applied on ADC0 pin, while AT command “AT+QEADC” can read the voltage value applied on ADC1 pin. For details of this AT command, please refer to the document [1]. In order to improve the accuracy of ADC, the layout of ADC should be surrounded by ground.
M50 Hardware Design 4. Change to HIGH when SMS is received. SMS When a new SMS comes, the RI changes to LOW and holds low level for about 120 ms, then changes to HIGH. URC Certain URCs can trigger 120ms low level on RI. For more details, please refer to the document [1] If the module is used as a caller, the RI would maintain high except the URC or SMS is received. On the other hand, when it is used as a receiver, the timing of the RI is shown below.
M50 Hardware Design HIGH RI 120ms LOW Idle or Talking URC or SMS received l te Figure 46: RI behavior of URC or SMS received c l c a i e t u n Q fide n o C M50_HD_V2.
M50 Hardware Design 3.16. Network status indication The NETLIGHT signal can be used to drive a network status indicator LED. The working state of this pin is listed in the following table. Table 28: Working state of the NETLIGHT State Module function Off The module is not running. 64ms On/ 800ms Off The module is not synchronized with network. 64ms On/ 2000ms Off The module is synchronized with network. 64ms On/ 600ms Off GPRS data transfer is ongoing.
M50 Hardware Design VBAT 300R Module 4.7K STATUS l te 47K c l c a i e t u n Q fide n o C Figure 48: Reference design for STATUS M50_HD_V2.
M50 Hardware Design 4. Antenna interface The Pin 63 is the RF antenna pad. The RF interface has an impedance of 50Ω. Table 30: Pin definition of the RF_ANT Name Pin Description GND 61 Ground GND 62 Ground RF_ANT 63 RF antenna pad GND 64 Ground GND 65 Ground GND 66 Ground l te c l c a i e t u n Q fide n o C 4.1. RF reference design The reference design for RF is shown as below.
M50 Hardware Design GSM850/EGSM900 is <1dB. DCS1800/PCS1900 is <1.5dB. 4.2. RF output power Table 31: The module conducted RF output power Frequency Max Min GSM850 32.5dBm ±1dB 5dBm±5dB EGSM900 32.5dBm ±1dB 5dBm±5dB DCS1800 29.5dBm ±1dB 0dBm±5dB PCS1900 29.5dBm ±1dB 0dBm±5dB l te c l c a i e t u n Q fide n o C Note: In GSM850&EGSM900 GPRS 4 slots TX mode, the max output power is reduced by 2.5dB. This design conforms to the GSM specification as described in section 13.
M50 Hardware Design 4.5. RF cable soldering Soldering the RF cable to RF pad of module correctly will reduce the loss on the path of RF, please refer to the following example of RF soldering. l te c l c a i e t u n Q fide n o C Figure 50: RF soldering sample M50_HD_V2.
M50 Hardware Design 5. Electrical, reliability and radio characteristics 5.1. Absolute maximum ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of module are listed in the following table: Table 34: Absolute maximum ratings l te Parameter Min Max Unit VBAT -0.3 +4.73 V Peak current of power supply 0 2 A RMS current of power supply (during one TDMA- frame) 0 0.7 A Voltage at digital pins -0.3 3.3 V Voltage at analog pins -0.3 3.
M50 Hardware Design 5.3. Power supply ratings Table 36: The module power supply ratings Parameter Description Conditions Min Typ Max Unit VBAT Supply voltage Voltage must stay within the min/max values, including voltage drop, ripple, and spikes. 3.3 4.0 4.6 V Vdrop during Maximum power control level transmitting burst on GSM850 and GSM900.
M50 Hardware Design DCS1800/PCS19002) Peak supply current (during 420/470 Maximum power control level on GSM850 and GSM900. 1.6 mA 1.8 A transmission slot) 1) 2) Power control level PCL 5 Power control level PCL 0 5.4. Current consumption The values of current consumption are shown as below.
M50 Hardware Design DATA mode, GPRS ( 3 Rx, 2 Tx ) CLASS 12 GSM850 @power level #5 <550mA,Typical 435mA @power level #12,Typical 158mA @power level #19,Typical 99mA EGSM 900 @power level #5 <550mA,Typical 400mA @power level #12,Typical 150mA @power level #19,Typical 97mA DCS 1800 @power level #0 <450mA,Typical 313mA @power level #7,Typical 130mA @power level #15,Typical 92mA PCS 1900 @power level #0 <450mA,Typical 337mA @power level #7,Typical 140mA l te @power level #15,Typical 94mA c l c a i e
M50 Hardware Design EGSM 900 @power level #5 <660mA,Typical 560mA @power level #12,Typical 215mA @power level #19,Typical 114mA DCS 1800 @power level #0 <530mA,Typical 420mA @power level #7,Typical 173mA @power level #15,Typical 97mA PCS 1900 @power level #0 <530mA,Typical 470mA @power level #7,Typical 192mA @power level #15,Typical 101mA l te Note: GPRS Class 12 is the default setting. The module can be configured from GPRS Class 1 to Class 12 by “AT+QGPCLASS”.
M50 Hardware Design 6. Mechanical dimensions This chapter describes the mechanical dimensions of the module. 6.1. Mechanical dimensions of module l te c l c a i e t u n Q fide n o C Figure 51: M50 top and side dimensions M50_HD_V2.
M50 Hardware Design l te c l c a i e t u n Q fide n o C Figure 52: M50 bottom dimensions M50_HD_V2.
M50 Hardware Design 6.2. Recommended footprint without bottom centre pads l te c l c a i e t u n Q fide n o C frame line silkscreen Figure 53: Recommended footprint without bottom centre pads M50_HD_V2.
M50 Hardware Design 6.4. Top view of the module l te c l c a i e t u n Q fide n o C Figure 54: Top view of the module M50_HD_V2.
M50 Hardware Design 6.5. Bottom view of the module l te c l c a i e t u n Q fide n o C Figure 55: Bottom view of the module M50_HD_V2.
M50 Hardware Design 7. Storage and manufacturing 7.1. Storage M50 is distributed in vacuum-sealed bag. The restriction of storage condition is shown as below.
M50 Hardware Design 7.2. Soldering The squeegee should push the paste on the surface of the stencil that makes the paste fill the stencil openings and penetrate to the PCB. The force on the squeegee should be adjusted so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil at the hole of the module pads should be 0.2mm for M50 .
M50 Hardware Design ℃ Heating Preheat Cooling 250 Liquids Temperature 217 200℃ 200 40s~60s 160℃ 150 70s~120s 100 l te c l c a i e t u n Q fide n o C Between 1~3℃/S 50 0 50 100 150 200 250 300 s Time(s) Figure 57: Ramp-Soak-Spike reflow profile 7.3. Packaging M50 modules are distributed in trays of 20 pieces each. This is especially suitable for the M50 according to SMT processes requirements. The trays are stored inside a vacuum-sealed bag which is ESD protected.
M50 Hardware Design Appendix A: GPRS coding schemes Four coding schemes are used in GPRS protocol. The differences between them are shown in Table 39. Table 39: Description of different coding schemes Scheme Code USF rate CS-1 1/2 3 Pre-coded Radio USF Block excl.USF and BCS 3 BCS 181 Tail 40 4 Coded Punctured Data bits bits rate Kb/s l te 456 0 9.05 c l c a i e t u n Q fide n o C CS-2 2/3 3 6 268 16 4 CS-3 3/4 3 6 312 16 4 CS-4 1 3 12 428 16 - 588 132 13.
M50 Hardware Design Appendix B: GPRS multi-slot classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependant, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
l te c l c a i e t u n Q fide n o C Shanghai Quectel Wireless Solutions Co., Ltd. Room 501, Building 13, No.99 Tianzhou Road, Shanghai, China 200233 Tel: +86 21 5108 6236 Mail: info@quectel.
