MPA-200/300 RS-422/485 SYNCHRONOUS ADAPTER CARD for ISA compatible machines INTERFACE CARDS FOR IBM PC/AT AND PS/2 User's Manual QUATECH, INC. 5675 Hudson Industrial Parkway Hudson, Ohio 44236 TEL: (330) 655-9000 FAX: (330) 655-9010 http://www.quatech.
Warranty Information Quatech Inc. warrants the MPA-200/300 to be free of defects for one (1) year from the date of purchase. Quatech Inc. will repair or replace any adapter that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights.
The information contained in this document cannot be reproduced in any form without the written consent of Quatech, Inc. Likewise, any software programs that might accompany this document can be used only in accordance with any license agreement(s) between the purchaser and Quatech, Inc. Quatech, Inc. reserves the right to change this documentation or the product to which it refers at any time and without notice.
Compliances - Electromagnetic Emissions EC - Council Directive 89/336/EEC This equipment has been tested and found to comply with the limits of the following standards for a digital device: EN50081-1 (EN55022, EN60555-2, EN60555-3) EN50082-1 (IEC 801-2, IEC 801-3, IEC 801-4) Type of Equipment: Information Technology Equipment Equipment Class: Commercial, Residential, & Light Industrial FCC - Class B This equipment has been tested and found to comply with the limits for a Class B digital device, purs
TABLE OF CONTENTS 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 HARDWARE INSTALLATION . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 SCC GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Accessing the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Baud Rate Generator Programming ..................... 9 3.3 SCC Data Encoding Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Quatech Inc.
1 INTRODUCTION The Quatech MPA-200/300 is a single channel, synchronous serial communication port for systems utilizing the architecture of the IBM AT personal or compatible computers. The MPA-200 is RS-422 compatible. The MPA-300 has RS-485 data line drivers and receivers in place of the MPA-200's RS-422 drivers and receivers. The MPA-300's RS-485 interface will allow multiple systems to be connected in a multi-drop configuration.
Figure 1 MPA-200 board drawing Quatech, Inc. MPA-200 U29 U9 U4 U10 U5 U11 U6 U12 U2 U7 U13 SW1 SW2 U3 U26 J4 3 J5 U23 CN1 CN2 J8 U18 U28 U14 U15 U8 U22 U17 J7 U1 U16 X1 J10 J11 U19 U24 U20 U25 U21 J6 Quatech Inc.
2 HARDWARE INSTALLATION If the default address and interrupt settings are sufficient, the MPA-200 can be quickly installed and put to use. The factory default settings are listed below in Table 1. Table 1 Default Board Configuration Address 300 hex Interrupt IRQ 5 TxDMA DMA/DRQ 3 RxDMA DMA/DRQ 1 1.
3 SCC GENERAL INFORMATION The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPA-200 provides a single channel for communications, however, to provide full DMA capabilities, both channels of the SCC can be utilized. The SCC can be software configured to satisfy a wide variety of serial communications applications.
3.1 Accessing the registers The mode of communication desired is established and monitored through the bit values of the internal read and write registers. The register set of the SCC includes 16 write registers and 9 read registers. These registers only occupy four address locations, which start at the MPA-200's physical base address that is configured via the on board switches. This and all other addresses are referenced from this base address in the form Base + Offset.
Example 3: Write data into the transmit buffer of channel A. mov out Example 4: dx,base dx,al ; load base address ; write data in ax to buffer Read data from the receive buffer of channel A. mov in dx,base al,dx ; load base address ; write data in ax to buffer Table 2 SCC read register description.
clock (TCLK) and the RTXC pin for its receive clock (RCLK). Programming of the clocks should be done before enabling the receiver, transmitter, BRG, or DPLL. Table 3 SCC write register description.
3.2 Baud Rate Generator Programming The baud rate generator (hereafter referred to as the BRG) of the SCC consists of a 16-bit down counter, two 8-bit time constant registers, and an output divide-bytwo. The time constant for the BRG is programmed into WR12 (least significant byte) and WR13 (most significant byte). The equation relating the baud rate to the time constant is given below while Table 4 shows the time constants associated with a number of popular baud rates when using the standard MPA-200 9.
3.3 SCC Data Encoding Methods The SCC provides four different data encoding methods, selected by bits D6 and D5 in WR10. These four include NRZ, NRZI, FM1 and FM0. The SCC also features a digital phase-locked loop (DPLL) that can be programmed to operate in NRZI or FM mode. Also, the SCC contains two features for diagnostic purposes, controlled by bits in WR14. They are local loopback and auto echo.
4 JUMPER BLOCK CONFIGURATIONS The MPA-200 utilizes seven user-selectable jumper blocks , that allow the user more flexibility when configuring the board. The following section explains the function of each of the jumper blocks on the MPA-200. 4.1 J4 - Interrupt Configuration J4 is a three pin jumper which determines whether or not a board’s interrupt is sharable. By selecting pins 1 & 2, the user has the ability to share an interrupt with other Quatech expansion cards.
4.3 IRQ10 1&6 IRQ11 2&7 IRQ12 3&8 IRQ14 4&9 IRQ15 5&10 J10 - Transmit DMA Channel Selection J10 selects the DMA channel to be used for transmit DMA. Three channels (1 - 3) are available on the MPA-200 for DMA. When selecting a DMA channel, both the DMA acknowledge (DACK) and the DMA request (DRQ) for the appropriate channel need to be selected. Table 8 summarizes the jumper block selections for J10 Table 8 Jumper block J10 selections.
4.4 J11 - Receive DMA Channel Selection J11 selects the DMA channel to be used for receive DMA. Three channels (1 - 3) are available on the MPA-200 for DMA. When selecting a DMA channel, both the DMA acknowledge (DACK) and the DMA request (DRQ) for the appropriate channel need to be selected. Table 9 summarizes the jumper block selections for J11. Table 9 Jumper block J11 selections.
Table 10 Jumper block J7 connections Driver Control Function Transmitter Always Enabled Transmitter controlled by Comm. Register Receiver Always Enabled Receiver controlled by Comm. Register 4.6 Pins 1&2 2&3 4&5 5&6 J8 - SYNCA to RLEN control J8 controls the signal path from the RLEN bit in the Communications register to the SYNCA input to the SCC. If J8 is installed the RLEN bit may be used to control the SYNCA pin when the SCC is in external SYNC mode.
5 ADDRESSING The MPA-200 occupies a continuous 8 byte block of I/O addresses. For example, if the base address is set to 300H, then the MPA-200 will occupy address locations 300H-307H. The base address of the MPA-200 may be set to any of the first 64 Kbytes (0 - FFFFH) of available I/O address space through the settings of dip switches SW1 and SW2. SW1 allows the user to select the higher address signals A15 - A8. SW2 allows the user to select the lower address signals A7 A3.
The first four bytes, Base+0 through Base+3, of address space on the MPA-200 contain the internal registers of the SCC. The next two locations Base+4 and Base+5 contain the communications register and the configuration register. The last two address port locations are reserved for future use. The entire address range of the MPA-200 is shown in Table 12.
6 INTERRUPTS The MPA-200 supports eleven interrupt levels: IRQ2 -7, IRQ10 - 12, and IRQ14 - 15. The interrupt level is selected through jumper blocks J5 and J6 ( see JUMPER BLOCK CONFIGURATIONS on page 11). The interrupt source is selected by bits D4 and D5 of the configuration register. The MPA-200 has three interrupt sources: interrupt on terminal count, interrupt on test mode, and interrupt from the SCC. Interrupts from the SCC can occur on a number of conditions, depending on which is programmed.
7 DIRECT MEMORY ACCESS Direct Memory Access (DMA) is a way of directly transferring data to and from memory, resulting in high data transfer rates with very low CPU overhead. The MPA-200 allows the user to perform DMA transfers when data is received (DMARRQ) or when data is transmitted (DMATRQ). Three different DMA channels are available(DMA1 - DMA3). Which channels are selected is determined by setting jumper blocks J10 and J11 (See Table 8, and Table 9).
of the SCC, a DMA request is generated. The DMA controller then writes the data from the SCC into memory. Programming for DMA request on both transmit and receive is simply a combination of the two. There are three possible configurations that can be used, depending on the sources selected. The first configuration available uses the W/REQA pin of channel A for DMA request on receive, and the DTR/REQA pin of channel A for DMA request on transmit.
Figure 3 Block diagram of DMA on MPA-200. J10 W/REQA DTR/REQA DMATRQ W/REQB DRMRRQ J11 PAL SCC 7.1 Using Terminal Count to Generate an Interrupt The MPA-200 allows the option of generating an interrupt whenever the Terminal Count (TC) signal is asserted. Terminal Count is an indicator generated by the system’s DMA controller, which signals that the number of transfers programed into the DMA controller’s transfer register have occurred.
8 CONFIGURATION REGISTER The MPA-200 is equipped with an onboard register used for configuring information such as DMA enables, DMA sources, interrupt enables, and interrupt sources. Below is a detailed description of the configuration register. The address of this register is Base+5. Table 13 details the bit definitions of the configuration register. Table 13 Configuration Register - Read/Write D7 D6 D5 0 0 INTS1 D4 D3 D2 D1 D0 INTS0 DMREN DMTEN RXSRC TXSRC D7-D6 Reserved, always 0.
D1 -RXSRC, RECEIVE DMA SOURCE: When set (logic 1), this bit allows the source for receive DMA to come from the W/REQB pin of channel B on the SCC. When cleared (logic 0), the source for receive DMA comes from the W/REQA pin of channel A on the SCC. D0 -TXSRC, TRANSMIT DMA SOURCE: When set (logic 1), this bit allows the source for transmit DMA to come from the DTR/REQA pin of channel A on the SCC. When cleared (logic 0), the source for transmit DMA comes from the W/REQA pin of channel A on the SCC.
9 COMMUNICATIONS REGISTER The MPA-200 is equipped with an onboard communications register which gives the user options pertaining to the clocks and testing. The user can specify the source and type of clock to be transmitted or received. Test mode bits pertain only to the DTE versions and can be ignored if using a MPA-200 configured DCE. The address of this register is Base+4. Table 14 and the descriptions that follow detail the communications register.
D3 -RECEIVE CLOCK ENABLE (DCE only): When set (logic 1), this bit allows the DCE to transmit its receive clock (RCLK). When cleared (logic 0), the DCE receives its RCLK. Since a DTE can only receive its RCLK, writing to this bit has no effect on a DTE. D2 -TRANSMIT CLOCK ENABLE (DTE only): When set (logic 1), this bit allows the DTE to transmit its transmit clock (TCLK). When cleared (logic 0), the DTE receives its TCLK. Since a DCE can only transmit its TCLK, writing to this bit has no effect on a DCE.
10 DTE / DCE Configuration The MPA-200 can be purchased in either Data Terminal Equipment (DTE) or Data Communications Equipment (DCE) configuration. The two configurations share some important features, but have significant differences which need to be mentioned. Both the DTE and DCE configurations allow the user to enable and disable the driver circuitry on the MPA-200 through the settings of jumper block J7.
10.1 DTE Configuration The control signals that the DTE can generate are the Request To Send (RTS) and Data Terminal Ready (DTR). It can receive the signals Carrier Detect (CD), Clear to Send (CTS), and Data Set Ready (DSR). All of the control signals are controlled through channel A of the SCC, with the exception of the DSR signal, which is received on channel B.
10.2 DCE Configuration On the MPA-200, the difference between the DTE and DCE signals is that, with the exception of a few control signals, the pins used for signal transmission on the DTE are used for signal reception on the DCE and vice versa. For example, pin 2 of the DCE connector is received data, yet the corresponding DTE signal is the transmitted data. This allows the user to connect a DTE device to a DCE device and perform communication without the use of any customized cable or adapter.
Figure 3 DCE Clock Configuration RTXCA (RCLK) RTXCB RRCLK TRXCB RTCLK RCKEN TCKEN TRXCA (TCLK) TTCLK The Test Mode (TM) signal is always in the OFF condition and cannot be changed by the user. The Local Loopback (LL) and Remote Loopback (RL) test signals are not implemented on the DCE. Table 16 summarizes the signals on the DCE. Quatech Inc.
11 EXTERNAL CONNECTIONS When configured as a DTE, the MPA-200 uses a D-25 short body male connector (labeled CN2). When configured as a DCE, the MPA-200 uses a D-25 long body female connector (labeled CN1). Table 15 and Table 16 describe the pin out definitions for both connectors and Figure 6 and Figure 7 illustrate the pin-outs for each of the connectors..
Table 16 DCE Connector Pin Definitions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal No Connect +RXD +TXD +CTS +RTS +DTR DGND +CD -TTCLK -CD -RRCLK -RTCLK -RTS -RXD +RTCLK -TXD +TTCLK No Connect -CTS +DSR No Connect -DTR -DSR +RRCLK TEST MODE Quatech Inc.
Figure 4 MPA-200 DTE Output Connector -CTS 13 -RTCLK 12 -TTCLK 11 -CD 10 -RRCLK 9 +CD 8 DGND 7 +DSR 6 +CTS 5 +RTS 4 +RXD 3 +TXD 2 CGND 1 25 TEST MODE 24 +TTCLK 23 -DTR 22 -DSR 21 RLBK 20 +DTR 19 -RTS 18 LLBK 17 +RRCLK 16 -RXD 15 +RTCLK 14 -TXD Figure 5 MPA-200 DCE Output Connector +RXD 2 +TXD 3 +CTS 4 +RTS 5 +DTR 6 DGND 7 +CD 8 -TTCLK 9 -CD 10 -RRCLK 11 -RTCLK 12 -RTS 13 31 14 15 16 17 18 19 20 21 -RXD +RTCLK -TXD +TTCLK N/C -CTS +DSR N/C 22 23 24 25 -DTR -DSR +RRCLK TEST MODE Quatech Inc.
11.1 MPA-200 and EIA-530 Compatibility If the MPA-200 is to be connected with an EIA-530 device, it may be necessary to swap the +/- conductors on the TXD and RXD signals. 11.2 Null-Modem Cables The MPA-200 does not use a standard asynchronous PC serial port connector pin out. Typical off-the-shelf null-modem cables cannot be used with this card. Quatech Inc.
12 DEFINITION OF INTERFACE SIGNALS CIRCUIT AB - SIGNAL GROUND CONNECTOR NOTATION: DGND DIRECTION: Not applicable This conductor directly connects the DTE circuit ground to the DCE circuit ground. CIRCUIT CC - DATA SET READY (DSR) CONNECTOR NOTATION: +DSR,-DSR DIRECTION: From DCE This signal indicates the status of the local DCE by reporting to the DTE device that a communication channel has been established.
CIRCUIT DB - TRANSMIT ELEMENT TIMING (TxClk - DCE Source) CONNECTOR NOTATION: +RTCLK,-RTCLK DIRECTION: From DCE This signal, generated by the DCE, provides the DTE with element timing information pertaining to the data transmitted to the DCE. CIRCUIT DD - RECEIVER ELEMENT TIMING (RxClk - DCE Source) CONNECTOR NOTATION: +RRCLK,-RRCLK DIRECTION: From DCE This signal, generated by the DCE, provides the DTE with element timing information pertaining to the data transmitted by the DCE.
CIRCUIT CD - DTE READY (DTR) CONNECTOR NOTATION: +DTR,-DTR DIRECTION: To DCE This signal controls the switching of the DCE to the communication channel. The DTE will generate this signal to prepare the DCE to be connected to or removed from the communication channel. CIRCUIT LL - LOCAL LOOPBACK (LL) CONNECTOR NOTATION: LLBK DIRECTION: To DCE This signal provides a means whereby a DTE may check the functioning of the DTE/DCE interface and the transmit and receive sections of the local DCE.
CIRCUIT TM - TEST MODE (TM) CONNECTOR NOTATION: TEST MODE DIRECTION: From DCE This signal indicates to the DTE that the DCE is in a test condition. The DCE generates this signal when it has received a local loopback or remote loopback signal from the DTE. Quatech Inc.
13 SPECIFICATIONS Bus interface: IBM AT 16-bit bus Controller: Serial Communications Controller, 6 MHz (determined by user, typically an Intel 82530). Physical Dimensions: 7.65” x 4.
MPA-200/300 User's Manual Version 5.31 March 2004 Part No.
