User`s manual

The choice of using the interrupt status register or the UART scratchpads
(factory default) is made using position 6 of switch SW2 as shown in
Figure 7.
Figure 7 --- Enabling the Interrupt Status Register
When a hardware interrupt occurs, reading the interrupt status
register will return the interrupt status of the entire QS/ES-100M, as
shown in Figure 8. Individual bits are cleared as the interrupting ports are
serviced. The interrupt service routine must ensure that the interrupt
status register reads zero before exiting, or the QS/ES-100M will be
unable to signal subsequent interrupts.
If the QS/ES-100M is of revision level 'B' or higher, an I/O write to
the interrupt status register will cause another hardware interrupt to be
generated if the interrupt status register is non-zero. The value written is
ignored and has no effect on the contents of the interrupt status register.
Software written to take advantage of this retriggering will be transparent
to an older revision of the QS/ES-100M.
BIT DESCRIPTION
7 (MSB) Serial 8 --- 1 if interrupt pending (always 0 on QS-100M)
6 Serial 7 --- 1 if interrupt pending (always 0 on QS-100M)
5 Serial 6 --- 1 if interrupt pending (always 0 on QS-100M)
4 Serial 5 --- 1 if interrupt pending (always 0 on QS-100M)
3 Serial 4 --- 1 if interrupt pending
2 Serial 3 --- 1 if interrupt pending
1 Serial 2 --- 1 if interrupt pending
0 Serial 1 --- 1 if interrupt pending
Figure 8 --- Interrupt Status Register contents
ON
1 2 3 4 5 6
SW2
ON
1 2 3 4 5 6
SW2
Slide position 6 of SW2 toward the top of the QS/ES-100M to enable the
interrupt status register, or toward the bottom of the QS/ES-100M to disable it.
Scratchpad Register
(factory default)
Interrupt Status Register
Quatech QS-100M/ES-100M User's Manual 9